16:01 <riscit> there is some fork of openocd for risc-v around, i guess that means the latest release of openocd in the average linux distro repo does not support risc-v ?

16:07 <PaulFertser> riscit: it does but probably in a limited way.

16:08 <riscit> PaulFertser: more limited than the fork?

16:31 <PaulFertser> riscit: yes, the riscv fork should have better support for riscv than the code that's currently upstream.

16:48 <riscit> What target file would I use best in this case. I have a Segger J-Link and already figured out the pins and device-ID with jtagulator. But i'm not familiar with openocd. Does it have some kind of generic risc-v target? I did not have any success with the software from Segger.

17:06 <PaulFertser> riscit: try gd32vf103.cfg for starters

17:39 <jtag-troubles> Hi all, I am reversing a device and trying to get JTAG working, I have determined the pinout and can go so far as to communicate with and read out the DAP. However, when I attempt to halt the processor I get an error saying: timeout waiting for DSCR bit change timeout waiting for DSCR bit change

17:39 <jtag-troubles> Config File: https://pastebin.com/V58dn97S

17:39 <jtag-troubles> DAP Info: https://pastebin.com/QmkyhC5f

17:39 <jtag-troubles> Logfile: https://pastebin.com/kDLn53xD

17:40 <jtag-troubles> I'm wondering if JTAG has been disabled on this CPU - it's a qualcomm MDM series SoC

17:40 <jtag-troubles> If anyone has any insights at all, I would really appreciate it! If not, no worries, I can't thank you folks enough for working on this tool!

17:49 <bencoh> jtag-troubles: does dap info work for the main processor AP?

17:50 <bencoh> (I'd expect it to be AP 1 on that kind of SoC, but who knows)

17:51 <bencoh> ah, nevermind :)

18:05 <jtag-troubles> I believe so! It seems to be working for the ARM core

18:07 <jtag-troubles> But aside from reading the DAP via dap info, I can't do much else

18:09 <jtag-troubles> JLink reports the following if it's helpful: https://pastebin.com/1USGyZcZ

18:31 <bencoh> is it supposed to be a cortex-a5?

18:33 <jtag-troubles> Yeah, according to an upstream dtsi file I found: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/qcom-mdm9615.dtsi

18:35 <jtag-troubles> It also mentions A5 in the ROM table as well

18:37 <bencoh> yeah

18:38 <bencoh> what about poking around the memory bus? you can define an ahb target in openocd and start reading from registers with mdw

18:39 <bencoh> (it would be AP 0)

18:40 <jtag-troubles> I can certainly try that, I'm wondering if debugging has been disabled in this scenario.

18:41 <bencoh> could be

18:42 <bencoh> or maybe you need to input a jtag password in some register first

18:42 <bencoh> into*

18:43 <jtag-troubles> Definitely, is it normal to always be able to access the DAP, but not necessarily the actual debugging features?

18:43 <bencoh> ah, I forgot something

18:43 <bencoh> idle

18:43 <bencoh> your A5 core might be idling

18:49 <jtag-troubles> Oh interesting, is there a specific way to "wake it up" or is that going to be platform dependent?

18:56 <bencoh> on linx you usually disable the cpuidle states

18:57 <bencoh> (in /sys/devices/system/cpu*/cpuidle/state* or something along those lines)

20:40 <jtag-troubles> Even with an AHB target defined and selected, I still cannot read memory