_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<joseng> Hi all, I try to use the HDMI ports of my NeTV2 board (Artix7 35T). When I add the colorbars example it works withour problems. But when I want to use the framebuffer, I get a lot of timing errors during synthesis/routing. Do I need to take care somehow about CDC from cd_sys to cd_hdmi? In all the examples in the litex_boards, there is nothing in d
<joseng> irection of extra CDC.
<joseng> I saw the add_video_framebuffer() functions checks a bunch of stuff and adds CDC related stuff, but this does not seem to be whats needed. It seems signals of the CSR registers of the video timing generator and the DMA Reader are failing. And also signals from the DMA reader to the DDR RAM
<joseng> If it helps, I'm happy to share the files and synth/route result outputs
<joseng> And it does not matter if I use 800x600@60Hz or 1920x1080@60Hz or 1920x1080@30Hz. The timing always fails. I get a video output, but it is definitely not correct. I get vertical bars with spacing instead of a solid screen with the color I write to RAM. But the color is correct and the image changes when I write data to RAM, so this all works. I gue
<joseng> ss the incorrect image content also comes from CDC issues.
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<whitequark[cis]> which paths are failing?
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