_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<joseng> whitequark[cis]: thanks for the hint. I tried a bit this morning, but did not get all the way to no timing violations. In the hdmi5x clock domain I have a few violations with -1ps. Will visit this next week again
<joseng> The sys_clk<>hdmi_clk are more or less not related. Only in a way, that a LiteDMAReader fetches data from the DDRAM in the sys_clk domain. But I think I saw somewhere in the litex code some CDC stuff. Need to take a look at that again
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