00:57 <sajattack> thanks for the tip _florent_

00:59 <cr1901> yea matrix bridge is working now... I think

00:59 <sajattack> oh sweet?

01:00 <sajattack[m]> hello from matrix?

01:01 <sajattack> it seems like it's one way

01:02 <sajattack> or maybe not, but my "hello from matrix" was the first message in the channel

01:02 <cr1901> I saw it

01:08 <sajattack[m]> yeah seems good now, I'm just not sure why there were no other messages at first, was it just turned on the second after you mentioned it? Or was it not activated until I joined it?

01:08 <sajattack[m]> I guess the latter could be logical

01:14 <cr1901> maybe it bridge had to be turned on

05:31 <shoragan[m]> The matrix bridge is working, but they are still tuning and debugging. (see #libera-matrix)

06:40 <_florent_> q3k, tmbinc: Thanks, that's just the continuation of your previous work with more reuse of LiteX's components :)

06:42 <_florent_> scopehal support is the long term goal indeed, I'll first continue working on the ADC/Frontend/VGA configuration a bit, then will try to import the capture data in glscopeclient

06:43 <_florent_> once this is working, we could try to add libscopehal support

07:04 <ysionneau1> o/ _florent_

09:16 <_florent_> zyp: https://github.com/enjoy-digital/litex/commit/ad1fe143cc32017589976b0934ffe73e696af9e4 adds an add_auto_tx_flush method to UART to avoid stalling the CPU when the source is not ready (as we discussed a few weeks ago)

09:19 <_florent_> ex in the scope project we want to let the CPU initialize the DRAM and don't want to stall it until we flush the UART over the Etherbone bridge

09:19 <_florent_> https://github.com/360nosc0pe/scope/commit/2d272911657f6adee32f0719efc18065514d9741

09:19 <zyp> nice

13:37 <shoragan> where should i look if i get "bios.elf: error: PHDR segment not covered by LOAD segment"? is the bios too large?