10:48 <tinybronca[m]> Hi all, do any Rockchip SOCs have microcode as part of their operation, either updatable or not? I heard claims some ARM SOCs have microcode like Intel CPUs https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/

10:56 <robmur01> None of Arm's CPUs have microcode

11:17 <tinybronca[m]> Interesting I guess you cannot believe everything you read then

11:21 <mps> tinybronca[m]: heh, I never trust in anything

11:22 <mps> always ask myself did I read it correctly and did the author write it correctly, and a lot of such questions

11:22 <mps> s/write/wrote/

11:23 <mps> old crypto people saying "in God we trust, everything else we check with pgp"

12:37 <hanetzer> think the closest thing they have to microcode is trusted firmware I guess.

12:37 <mps> well, these are different things

12:38 <hanetzer> true, I guess trusted firmware is more akin to the ME firmware in a sense, and literally the psp firmware since the psp is an arm secure proc

12:39 <mps> yes, firmware is executed by cpu, but microcode goes in cpu and controls cpu executions of instructions

12:41 <lurchi_> It is probably part of the CISC-microcode translation step, and and RISC processor typically wont have that step

12:41 <mps> right

12:42 <mps> ciscs usually have microcode while riscs doesn't, in theory at least

12:42 <mps> but I'm not sure nowadays, maybe some riscs also have microcode

15:27 <CounterPillow> modern ARM isn't RISC

15:35 <robmur01> it never was really, only RISC-inspired. Just look at the "load several registers, update the base register, branch and change the processor mode" instruction that was there from day 1 ;)

15:43 <robmur01> but indeed more modern ISAs (e.g. AArch64) tend to be designed as compiler targets rather than for hand-written assembly, so the RISC/CISC distinction is even more blurred and less relevant

16:34 <mps> CounterPillow: yes, I know they are not RISC, I call arm as 'RISC like'

16:35 <mps> long ago I designed industrial computer with 6502 which is some kind of arm predecessor

17:17 <tinybronca[m]> mps: Do IBM Power ISA CPUs have microcode?

18:10 <mps> tinybronca[m]: I didn't worked with them so not sure but I think it has. Take this with grain of salt

18:13 <mps> though they told it is 'true RISC' so it shouldn't have it

18:15 <mps> I think RISC-V doesn't have microcode (so or better called microprogramming)

18:17 <mps> if the RISC follow principle of 'single-cycle single instruction' then it shouldn't have microcode

18:31 <CounterPillow> whether or not something is microcoded is entirely down to the implementation of the core, not the ISA itself

18:32 <mps> yes, ISA is not relevant to this