03:58 <chewitt> last time I looked the BPI sources were [badly] hacked copies of the hardkernel sources

07:22 <narmstrong> My priorities are: finishing Linux DSI support, setup automated u-boot and Linux CI and after I’ll probably resume my DSI work on u-boot to have early boot display on the reform laptop

09:17 <minute> narmstrong: oh, u-boot DSI would be lovely!

09:18 <narmstrong> I have a very old branch with support implemented, I need to resync with how I reworked in on linux

09:19 <narmstrong> I rebased it earlier this year https://github.com/superna9999/u-boot/commits/u-boot/axg-dsi

09:20 <narmstrong> it was for AXG, so G12/SM1 changes needs to be added

09:23 <minute> narmstrong: this is our all-in-one driver for the uboot display on imx8m, which includes code for the edp bridge https://source.mnt.re/reform/reform-boundary-uboot/-/blob/master/board/boundary/nitrogen8m_som/lcdif.c?ref_type=heads

09:24 <minute> iirc it was also upstreamed

09:25 <narmstrong> minute: nice, somehow the bridge code should be copied out

10:56 <f_> chewitt: yeah looks like a hacked up copy of hardkernel/khadas source code

11:01 <chewitt> f_ actually I think BPI borrowed both depending on which board they cloned

11:02 <chewitt> the SM1 boards use HK sources, the G12B boards use Khadas

11:04 <f_> Yeah seems like.

11:11 <f_> Nontheless I'll probably clone the repo mainly for looking at the acs structs

11:13 <f_> Just like what I've been doing for the librecomputer sources

11:13 <f_> they're good...but lack history :/

11:14 <f_> Radxa sources also include git history....but they're split into multiple repos which is annoying

12:04 <djrscally> Hello all; so going back to the problem kbingham raised; I'm working with the Alta board with AML's A311D and trying to read the ISP's registers - base 0xff140000 which causes a panic. narmstrong told us we'd need the cts_mipi_isp_clk enabled - that seems not to be driven by the g12a-clkc clock driver so it's not

12:05 <djrscally> not something we can just add to dt unless I'm missing something *

12:07 <djrscally> I did try enabling it with rwmem; 0xff63c148[17]=0x1 and 0xff63c1c0[8]=1 but that didn't change what we get when reading the ISP's registers. There is a section of the datasheet called "Power Sequence of ISP", does that need addressing too perhaps?

12:26 <narmstrong> Where did you find this section ? I never got it

13:02 <pinchartl> narmstrong: https://dl.khadas.com/hardware/vim3/datasheet/a311d_datasheet_01_wesion.pdf

13:03 <pinchartl> page 96

13:03 <djrscally> There's a newer version

13:03 <djrscally> s/01/08

13:03 <pinchartl> (marked as 87 in the PDF)

13:04 <pinchartl> https://dl.khadas.com/hardware/vim3/datasheet/a311d_datasheet_08_wesion.pdf

13:06 <narmstrong> wait, I was looking in the registers not in those sections...

13:19 <jbrunet> djrscally: some gates might be missing. feel free to submit a patch if you know where a gate is missing, I'll happily apply it. That seems to be the case for mipi_clk ( 0xff63c148[17]=0x1)

13:23 <jbrunet> The other you clock you mentioned ( 0xff63c1c0[8]=1 ) seems to be the gate of a composite (mux / div / gate) clock called "cts_mipi_isp_clk" . I dunno if this used clock the register or simply used to drive something while the IP is already working. What is sure is that you need to deal with divider and multipler part as well to get something out of this clock

13:26 <jbrunet> You'll need to set the rate with this one ... it is not just a plain gate that you turn on and forget about

13:26 <jbrunet> Note that the datasheet should be taken with grain of salt. There is lot of copy/paste involved from SoC to SoC so it is not always 100% reliable. Digging in the vendor code (such as the ones found khadas or odroid github's) is another useful of information

13:29 <kbingham> jbrunet, As we don't know this SoC architecture at all - and our focus is on the ISP ... is it possible for you and narmstrong to help with this bit at all please? I dno't want us to spend days trying to figure out how to enable and upstream power domains and clocks ... when we should be working out how to drive the ISP. (If I'm wrong please correct me, but I assume this is an 'easy' patch for someone who has already worked on the

13:29 <kbingham> clock trees and power domains on the platform - but we'd be starting from scratch)

13:30 <narmstrong> djrscally: pinchartl: please test those changes, it includes the pmdomain and the isp & PHY clock gates https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/amlogic/upstream/isp-pmdomain?ref_type=heads

13:30 <narmstrong> only build tested

13:30 <kbingham> narmstrong, I think you've answered my question ;-P Thanks!

13:32 <narmstrong> :-p

13:34 <kbingham> narmstrong, Thanks- even if it's not complete that's plenty of guidance ;-) It would definitely have taken me a day to find all those places!

13:35 <narmstrong> kbingham: sure, but it's only filling blanks for me, nothing new so it was easy

13:40 <djrscally> narmstrong: thanks! I'll give it a try

17:35 <f_> oh hi/whois pinchartl

17:35 <f_> whoops

17:36 <f_> oh hi pinchartl djrscally

17:36 <f_> Nice to see people already hacking on alta :)

17:45 <pinchartl> hi f_

17:45 <pinchartl> not hacking much on my side, beside getting the board to netboot on mainline :-)

17:46 <f_> That's what I call, hacking :)