00:15 <_whitenotifier-4> [glasgow] hcsch opened pull request #741: Add a 24 series I2C EEPROM emulator - https://github.com/GlasgowEmbedded/glasgow/pull/741

00:18 <hcsch> That's still a draft, but now the code is actually somewhere I can point at ^^

00:18 <hcsch> I'll try and get it into a more reviewable state in the next few days

00:20 <whitequark[cis]> gotcha. it would need to match the style and structure of the existing applets to be accepted

00:23 <hcsch> I've already tried doing keeping it that way as best I can, but addressing, events to the host, and docs are not quite finished yet

06:28 <biko1311[m]> Is it possible to have a Verilog module as part of an applet? This is for a personal project, so I'm not looking for official support. It's fine if this requires patching internal code 🙂

06:29 <whitequark[cis]> it is not

06:29 <whitequark[cis]> (well, it is possible with enough modifications, but it's not something i care about providing at all)

06:30 <whitequark[cis]> (note that the standard Amaranth platform.add_file() construct is just ignored in Glasgow)

06:31 <biko1311[m]> That's fair. Thanks for the quick response!

06:32 <whitequark[cis]> if you really want it you probably want to instantiate a GlasgowRevC123 platform and manually add applet logic and all the Verilog stuff the usual way you'd do it in Amaranth, then build the bitstream manually, then upload it also manually

06:33 <whitequark[cis]> but the built-in build system and its caching feature relies on knowing that there is nothing but Amaranth-generated RTL, and it will break if this is not true

06:34 <biko1311[m]> Yes, well I probably don't want it that much 😅