12:04 <whitequark[cis]> <anuejn> "hey, is there currently a way..." <- nope, but this is something I'm interested in building

12:05 <anuejn> cool :)

12:06 <anuejn> do you think working around that and using the amaranth infrastructure directly is viable (for something that I might want to upstream later)

12:07 <whitequark[cis]> so, I want to replace the Amaranth infrastructure upstream by prototyping it in Glasgow

12:07 <whitequark[cis]> I propose we collaborate on that and improve things for everyone

12:08 <anuejn> sounds good :)

12:08 <anuejn> what do you have in mind? what bothers you with the amaranth infra?

12:12 <whitequark[cis]> packing everything into .request that does not present many customization options; exposing inout wires in any way

12:13 <whitequark[cis]> basically, I want platform.request2 to return opaque objects that only record the location of a pin or what you have (thinking of SoC too, here) and then that opaque object would be used to construct an IO buffer, in a normal way rather than a special one that magically exists just for .request

12:51 <anuejn> ah huh, that sounds like quite a nice improvement

12:51 <anuejn> also for some other problems I had in the past

13:34 <whitequark[cis]> yep

13:46 <galibert[m]> Couldn’t request return a submodule with an interface ?

13:49 <galibert[m]> which you'd have to += to the submodule member of course

13:52 <whitequark[cis]> nope, that breaks on intel platforms that require the iobuf to be in the top module for some cursed reason

13:53 <galibert[m]> the bugs of quartus should not define the amaranth language :-)

13:55 <whitequark[cis]> not being able to use DDR IO on Intel platforms is a showstopper

13:56 <whitequark[cis]> in any case, the plan is for the IO buffer to instantiate itself and add itself to wherever it's appropriate to have it

13:56 <galibert[m]> Of course not, but if the constraint is "put that submodule at top level" you can generate the verilog that way without changing the amaranth-side netlist

13:56 <galibert[m]> It's kind of a quartus quirk

13:56 <whitequark[cis]> can you?

13:57 <galibert[m]> it's just a renaming at generation time, isn't it?

13:57 <galibert[m]> I may not be understanding enough, of course

13:57 <whitequark[cis]> not really, it's a much more complex netlist transformation

13:57 <whitequark[cis]> or it would have been defined that way already

13:57 <whitequark[cis]> you are missing the forest for the tree, anyway

13:57 <galibert[m]> probably

13:57 <whitequark[cis]> the thing is that we do not know what kind of quirks which platforms will have

13:58 <whitequark[cis]> so locking ourselves into "an IO buffer is a single submodule that can be inserted anywhere in the hierarchy" is a bad idea

13:58 <whitequark[cis]> it should be instantiated by the platform wherever the platform deems it necessary

23:58 <_whitenotifier-f> [glasgow] anuejn opened pull request #490: More performant logic analyzer applet - https://github.com/GlasgowEmbedded/glasgow/pull/490