dgilmore changed the topic of #fedora-riscv to: Fedora on RISC-V https://fedoraproject.org/wiki/Architectures/RISC-V || Logs: https://libera.irclog.whitequark.org/fedora-riscv || Alt Arch discussions are welcome in #fedora-alt-arches
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<davidlt[m]> Ech, had to rebuild qt5-base to solve some TEXTRELs. Sadly that also means a new qt5 version.
<davidlt[m]> Time to rebuild the whole QT5.
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<thefossguy> Where might i get a complete list of all instructions in rv64g?
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<thefossguy> I found the manual but am in the look for a cheatsheet of sorts XD
<thefossguy> Reading the manual now... TIL RISC-V has variable length instructions! (I wonder which extension(s) have those.)
<davidlt[m]> We don't have those IIRC.
<davidlt[m]> There is 16-bit if you implement compressed, otherwise it's 32-bit.
<davidlt[m]> Quick google also kind states similar. While there is possibility for 48-bit and 64-bit instructions, there are no extensions using it.
<davidlt[m]> In other words, 16/32/48/64 would be legal (notice each step is 16-bit wide).
<thefossguy> <davidlt[m]> "There is 16-bit if you implement..." <- So, are you talking about the C extension coming under the variable length instructions?
<davidlt[m]> Well yeah, ISA wise.
<davidlt[m]> But it's not Intel-like.
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