dgilmore changed the topic of #fedora-riscv to: Fedora on RISC-V https://fedoraproject.org/wiki/Architectures/RISC-V || Logs: https://libera.irclog.whitequark.org/fedora-riscv || Alt Arch discussions are welcome in #fedora-alt-arches
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<PrathamPatel[m]> Clock/Reset/DTS merged in -next for the RISC-V maintainer's fork
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<davidlt[m]> Yup, this finally landed for 6.4 kernel!
<davidlt[m]> More incoming.
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<neil> :D nice!
<davidlt[m]> The story begins again with Sipeed boards :D
<davidlt[m]> It took StarFive to get basic support in what? ~6 months?
<neil> heh yeaahhhh
<neil> 🤞for quick upstreaming
<davidlt[m]> To my knowledge SIpeed doesn't plan to do it.
<davidlt[m]> I don't know if Alibaba / T-HEAD will do anything too.
<davidlt[m]> Remember what happened with D1. A lot of that seems to be community effort.
<neil> :/
<davidlt[m]> I would assume that Sipeed stuff will replace StarFive boards as value option.
<davidlt[m]> I mean OoO cores, 16GB of RAM (also faster), T-HEAD extensions (not used right now) and for a similar price point.
<davidlt[m]> There is a patch to hook "fast unaligned access" IFUNCs in glibc for D1 (T-HEAD) using the new HW probe interface.
<davidlt[m]> That seems to improve performance on D1.
<davidlt[m]> All SiFive cores on the SBCs don't support unaligned accesses. Those are "extremely slow" if used as it's handled by OpenSBI.
<davidlt[m]> HW probe interface, IIRC, incl. 3 options for this one: fast (i.e. implemented in hardware), emulated (e.g. OpenSBI), not implemented.
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<cwt[m]> does the openssl / libressl already use crypto engine in kernel and thus (automatically) use the hardware crypto engine?
<davidlt[m]> I don't think so, but didn't investigate.
<cwt[m]> one of the CPU cores got 100% while rsync or scp.
<cwt[m]> And the bandwidth was so slow that I have to use ftp instead
<davidlt[m]> Yeah, the life of weak SoCs :)
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