dgilmore changed the topic of #fedora-riscv to: Fedora on RISC-V https://fedoraproject.org/wiki/Architectures/RISC-V || Logs: https://libera.irclog.whitequark.org/fedora-riscv || Alt Arch discussions are welcome in #fedora-alt-arches
<davidlt[m]> Anup:
<davidlt[m]> > We are close to the OpenSBI v1.2 release. I plan to complete this
<davidlt[m]> > release before the end of next week (i.e. 24th December 2022).
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<varlad[m]> davidlt: You were right!
<varlad[m]> Looks like most of the next round of RISCV SBCs will come with the V extension :D
<varlad[m]> JH8100 is based on Dubhe (and has the V extension)
<varlad[m]> * davidlt: You were right!
<varlad[m]> Looks like most of the next round of RISCV SBCs will come with the V extension :D
<varlad[m]> JH8100 is based on Dubhe (and has the V extension). I expect next VisionFive and some other boards to run on this :)
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<davidlt[m]> Yeah, there is (or will be) 16-core (a single chiplet) development platform.
<davidlt[m]> Otherwise IIUC they are doing custom chips for their customers.
<davidlt[m]> I think what they have is framework for these CPUs. Probably less detailed compared to what SiFive offers (like tweaking L2, etc.)
<davidlt[m]> It sounds that they are more on a large parts, like chiplets.
<davidlt[m]> It sounds like a custom AMD EPYC stuff.
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