23:14 <ddribin[m]> Hi all. I'm new to Amaranth and HDLs in general (mostly a software background) but I have done some Verilog. I'm using an iCEBreaker FPGA and I'd like to hookup the on-board button to the reset signal. I've tried this:... (full message at

23:14 <ddribin[m]> <https://catircservices.org/_irc/v1/media/download/AQud2OsD1AVxiyQxupnZdN4nfD9ArUfVB1fO_R023-_Df4NSJADOXSkIUyG2pp2rPvvDBimjm3abGYpaC6y-N6C_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9xb1lNU0FKa0JtdXVsU09pZlpRREREcmI>)

23:18 <vegard_e[m]> a driver conflict is when you're trying to drive a signal from multiple modules -- in other words, the reset signal you're trying to drive is already driven elsewhere

23:18 <vegard_e[m]> here: https://github.com/amaranth-lang/amaranth/blob/main/amaranth/vendor/_siliconblue.py#L425

23:18 <tpw_rules> there is some internal logic in the platform to reset the device specifically on ice40 yeah

23:19 <tpw_rules> you could use a submodule and a domainrenamer, or just a new clock domain

23:21 <whitequark[cis]1> if you create a "sync" domain manually the built in logic becomes inactive

23:21 <cr1901> https://github.com/cr1901/sentinel/blob/docs/examples/attosoc.py#L1012-L1013 You can also force a default reset (Idk if this is supported, but it works)

23:23 <whitequark[cis]1> it's a bit odd but seems fine to me