#amaranth-lang on 2025-01-20 — irc logs at libera.irclog.whitequark.org

2024-02-21 07:31 whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · play https://amaranth-lang.org/play/ · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org

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10:01 <RobTaylor[m]> <zyp[m]> "I'd argue that if UARTPhy..." <- i think i agree :)

10:02 <RobTaylor[m]> in case anyone here is interested, LATTE workshop on languages, tools, and techniques for accelerator design deadline in 2 weeks: https://capra.cs.cornell.edu/latte25/

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15:37 <jfng[m]> <zyp[m]> "I'd argue that if UARTPhy..." <- i did this to allow a peripheral wrapper to have a member with `UARTPhy.Signature` in its interface, without having to instantiate the phy itself

15:37 <jfng[m]> https://github.com/ChipFlow/imec-workshop/blob/e4983c05ee7a69efe73bb2750505046a236e13c2/riscv-demo/riscv_demo/ips/uart/periph.py#L85

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15:38 <whitequark[cis]1> oh I see

15:39 <jfng[m]> i agree that the inner signatures needing to be flipped in the UARTPhyRx/Tx constructors is awkward

15:41 <jfng[m]> iirc, the reason for `self.Signature.flip()` was that the data stream flowed from the bus to the PHY, so i oriented it an input

15:41 <jfng[m]> (https://github.com/ChipFlow/imec-workshop/blob/324a264a97c2785a69ac34bec678bd5496eb920e/riscv-demo/riscv_demo/ips/uart/phy.py#L23)

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