<SjefCoder>
two questions: 1, how do you pass the platform clk to another signal in the module? I tried m.d.sync += [module_clk.eq(~module_clk)], but the pulses are not equal in length to the platform clk. 2. in the Simulator vcd, why do I not see my Instance (that references a module in vhdl)?
<whitequark[cis]>
the simulator will not simulate any instances
<whitequark[cis]>
vhdl in particular is not even really planned
<SjefCoder>
I suspect I then have to convert the Amaranth module to verilog, then the vhdl to the verilog, and then I can use Icarus or verilator to create a simulation
<SjefCoder>
I wonder how people simulate all these various softcore cpus
<SjefCoder>
when they try to incorporate them in an Amaranth environment
<SjefCoder>
most often these come in verilog or vhdl