whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · play https://amaranth-lang.org/play/ · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<_whitenotifier-4> [rfcs] mndza commented on pull request #41: Add an RFC for fixed point types. - https://github.com/amaranth-lang/rfcs/pull/41#issuecomment-2514433816
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<SjefCoder> Hi, I cannot find in the docs (dev) any reference to how to use an existing vhdl file
<whitequark[cis]> which toolchain are you using?
<SjefCoder> I am using the Gowin platform
<SjefCoder> in Litex I am familiar with: platform.add_source
<whitequark[cis]> there's platform.add_file()
<whitequark[cis]> it's used like platform.add_file("foo.vhd", "architecture ...")
<whitequark[cis]> note that you supply the contents, not a path
<SjefCoder> ahhh, your last comment made me google
<SjefCoder> "    platform.add_file("my_verilog_design.v", open("path_to_my_verilog_design.v"))"
<SjefCoder> seems to accord with an "older" nmigen post
<SjefCoder> pasting it here for posterity
<whitequark[cis]> yeah, that works
<SjefCoder> thanks, I am myself making notes in Obsidian. Hopefully at some point I can publish them online as I figure out a meaningful way to use Amaranth in my projects
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<_whitenotifier-4> [amaranth-lang/rtl-debugger] whitequark pushed 1 commit to main [+0/-0/±3] https://github.com/amaranth-lang/rtl-debugger/compare/fce5805e5b07...7319295173c3
<_whitenotifier-4> [amaranth-lang/rtl-debugger] whitequark 7319295 - Add infrastructure to lazily parse CXXRTL packets.
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