<SjefCoder>
question, just for some clarification, how would you be able to listen to the rst pin in your module if your module complains that a request, i.e., platform.request has happened earlier in the code? I cannot do any kind of self.rst or something in order to access the signal
<whitequark[cis]>
sorry, I don't understand the question
<SjefCoder>
Apologies, so I have my own module. In the elaborate section, I request platform.request("rst")
<SjefCoder>
I cannot build the module, because I am getting an error that rst is a resource already requested
<SjefCoder>
I assume this is probably done in some other place that I am not aware of that utilizes "default_rst"
<whitequark[cis]>
ah, yes. if you don't define a "sync" clock domain then one will be defined for you, using default_clk and default_rst
<SjefCoder>
resulting in: amaranth.build.res.ResourceError: Resource rst#0 has already been requested
<SjefCoder>
I am thinking, because Amaranth is new to me, why is this a problem?
<SjefCoder>
Is it some kind of guard rail to prevent multiple modules driving a signal?
<whitequark[cis]>
in this case, it's just that any resource can be requested exactly once
<SjefCoder>
At one point I want a final state machine that reset values on...you guessed it...reset
<SjefCoder>
What would be an "Amaranth best practice"?
<SjefCoder>
when you use platform/board
<whitequark[cis]>
so if you want a state machine to reset on the sync clock domain reset, and the state machine is placed in that domain, it will happen automatically
<SjefCoder>
m.If( m or self.sync_domain_clk_rst?)
<whitequark[cis]>
I don't understand you again
<SjefCoder>
"it will happen automatically" < wait, I am trying to wrap my mind around this
<whitequark[cis]>
a state machine doesn't need to be explicitly reset on clock domain reset
<whitequark[cis]>
just like a Signal that is used as a register, it will get reset by the clock domain reset
<SjefCoder>
Signal(reset=99) < this I understand, because on reset this will autmatically go back to 99, but with fsm...hmm...interesting
<whitequark[cis]>
you can think of an FSM as something that has a state signal inside
<SjefCoder>
(I am still thinking in classic verilog where in most code you see like a section with an if condition followed by whatever_pin <= original_reset_value)
<whitequark[cis]>
yeah, that's not necessary in Amaranth
<SjefCoder>
Ah, got it
<SjefCoder>
Amaranth, is really interesting. Once you start using it as a Python dev, you just cannot go back...
<whitequark[cis]>
if you do need to do something on clock domain reset yourself, then with m.If(ResetSignal()): will do it
<whitequark[cis]>
but it's not necessary to add with m.If(ResetSignal()): m.next = "Initial-State" to all of your FSM states
<SjefCoder>
fascinating
<SjefCoder>
my whole quest started with the fact that my fpga board is only reset if I unhook the USB power and put it back in
<SjefCoder>
and then I thought: can't I just re-use one of the buttons to reset everything
<SjefCoder>
and then I thought: well, I obviously need an initial state
<whitequark[cis]>
yeah so all you need is to do default_rst = "rst_btn" or something
<whitequark[cis]>
if not specified, the first defined state becomes the initial state
<whitequark[cis]>
* not specified explicitly, the
<SjefCoder>
cool, thanks for taking the time to clarify
<whitequark[cis]>
no worries!
<SjefCoder>
should I implement a debounce for the button?
<SjefCoder>
I Googled nmigen debounce, litex debounce, amaranth debounce, just to get a feel of whether there was an example
<SjefCoder>
or is that over engineering?
<whitequark[cis]>
it's usually not very important to debounce reset since, well, it's reset
<whitequark[cis]>
resetting five times in a row has the same end result as once
<SjefCoder>
I guess you are right. Fyi, tried it out, works like a charm.
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<SjefCoder>
which cpu are people using with the dev version of amaranth (0.6)?