07:45 <_whitenotifier-3> [amaranth-lang/rfcs] whitequark pushed 11 commits to main [+2/-0/±9] https://github.com/amaranth-lang/rfcs/compare/be658d7c84d5...f4e3de1c3258

07:45 <_whitenotifier-3> [amaranth-lang/rfcs] zyp 52efa4d - RFC #66: Simulation time

07:45 <_whitenotifier-3> [amaranth-lang/rfcs] zyp dbb347f - RFC #66: Expand scope to also cover platform code dealing with clock constraints.

07:45 <_whitenotifier-3> [amaranth-lang/rfcs] zyp eac6b9f - RFC #66: Update according to feedback

07:45 <_whitenotifier-3> [amaranth-lang/rfcs] ... and 8 more commits.

07:45 <_whitenotifier-3> [rfcs] whitequark closed pull request #66: RFC #66: Simulation time - https://github.com/amaranth-lang/rfcs/pull/66

07:45 <_whitenotifier-3> [rfcs] whitequark commented on pull request #66: RFC #66: Simulation time - https://github.com/amaranth-lang/rfcs/pull/66#issuecomment-2257691219

07:45 <_whitenotifier-3> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+1/-0/±56] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/a77cb8007046...3a1cbe7cbe70

07:45 <_whitenotifier-3> [amaranth-lang/amaranth-lang.github.io] whitequark 3a1cbe7 - Deploying to main from @ amaranth-lang/rfcs@f4e3de1c3258957e948be3228b0f00975b25116b 🚀

12:50 <_whitenotifier-3> [amaranth-soc] jfng commented on issue #97: MemoryMap should allow adding windows with a larger granularity than the parent - https://github.com/amaranth-lang/amaranth-soc/issues/97#issuecomment-2258275236

18:20 <_whitenotifier-3> [amaranth-soc] zyp commented on issue #97: MemoryMap should allow adding windows with a larger granularity than the parent - https://github.com/amaranth-lang/amaranth-soc/issues/97#issuecomment-2258943210

22:53 <bl0x[m]> I'm updating a module from legacy Memory to the new Memory class (RFC 45). Do I have to use the new way of running simulations to properly simulate this new Memory? Or should the legacy simulation (with add_sync_process) still work?

22:55 <whitequark[cis]> the legacy simulations should still work

22:55 <whitequark[cis]> they're emulated on top of the new ones

22:59 <bl0x[m]> Hm, then for some reason I don't see anything on the read port.

23:07 <bl0x[m]> Oops, did not add the Memory to m.submodules...

23:07 <bl0x[m]> Works now.

23:08 <whitequark[cis]> there should be a warning for that

23:11 <bl0x[m]> Yes, in fact there was one. Above the backtrace. Meh, it's late.