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<zyp[m]>
<zyp[m]> "and I suppose the recommended..." <- the issue is that this is a situation that `MemoryMap` doesn't support
<zyp[m]>
ValueError: Window has data width 32, and cannot be added to a memory map with data width 8
<whitequark[cis]>
are you using the CSR bridge?
<whitequark[cis]>
that bridge has configurable data width, which is why this wasn't considered an issue
<zyp[m]>
sure, having an 8-bit wide CSR bus works fine
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<zyp[m]>
the issue is that since my initiator has a granularity of 8, everything has to have a granularity of 8 or less
<zyp[m]>
and since the CSR bus doesn't have byte enables, it's impossible to have a wider CSR bus than 8-bit
<whitequark[cis]>
yes, that sounds right to me
<whitequark[cis]>
it is not in general possible to split or coalesce memory accesses to I/O regions
<zyp[m]>
that's beside the point, I'm not interested in doing that
<whitequark[cis]>
the CSR bridge has some very specific constraints for how the bytes may be accessed because of that
<whitequark[cis]>
it's relevant: that's why the MemoryMap has this design
<zyp[m]>
my point is that I don't necessarily want a MMIO access from my 32-bit CPU to be serialized into four byte-wide accesses and then reassembled back to access a 32-bit register
<whitequark[cis]>
sounds like the core problem here is that the CSR bridge doesn't support granularity
<zyp[m]>
yeah, so I started writing a gasket to put between the CSR bridge and the wishbone interconnect
<whitequark[cis]>
or in other words: that the CSR bridge doesn't define a behavior for sub-word access
<whitequark[cis]>
I think it's fine (as in, likely desirable) that you can't write such a gasket
<whitequark[cis]>
memory mapped infrastructure isn't composable, if a driver is accessing a CSR in a particular way, it expects the access to do something very specific
<zyp[m]>
and then ran into the issue that MemoryMap doesn't have a way to translate a 32b granularity map into an 8b granularity map
<whitequark[cis]>
and if the CSR bridge doesn't define how to access the bus via some kind of interconnect, it's just undefined
<whitequark[cis]>
the right way to resolve this, I think, is to define what granularity means for the CSR bus ("only full width accesses are supported") and then add support for it to the CSR bridge
<zyp[m]>
that'd still have the same issue with MemoryMap
<whitequark[cis]>
would it?
<zyp[m]>
yes, because MemoryMap would have to multiply the resource addrs by 4 when doing the window translation, and currently it can only convert the other way
<whitequark[cis]>
we should discuss this on a workday
<zyp[m]>
because MemoryMap apparently doesn't distinguish between width and granularity, and what it calls width is really granularity
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<bl0x[m]>
Writing Amaranth feels so cozy. VHDL kind of the opposite.
<whitequark[cis]>
that is the direct intent
<bl0x[m]>
I know. And it makes me happy every time I think about that
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