<mcc111[m]>
Is it feasible to target Tiny Tapeout from amaranth or something amaranth can compile to? What additional skills would I need to pick up to achieve this?
<whitequark[cis]>
possible
<mcc111[m]>
👍
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<zyp[m]>
so the fundamental issue behind #1454 is that a signal can only be driven by a single module, am I getting that right? i.e. separate modules aren't allowed to write the same signal even though they're touching non-overlapping slices of it
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<Wanda[cis]>
correct
<Wanda[cis]>
(I intend to fix that issue very soon FWIW)
<zyp[m]>
soon enough that a workaround for SimulationPort would be pointless?
<zyp[m]>
that of course breaks all the test cases that expects the getters to return an actual signal, but it fixes the example in #1454
<zyp[m]>
(and yes, this is obvious enough that I'm not gonna be surprised if this was already considered and shot down)
<zyp[m]>
but it piqued my curiosity and gave me an opportunity to look into how SimulationPort was implemented
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<Wanda[cis]>
indeed we have already discussed it yesterday and came to this conclusion.
<Wanda[cis]>
there were several workarounds suggested, all of them unsatisfactory
<Wanda[cis]>
so I'm just going to fix the underlying issue and allow driving individial bits per-module, as it should be
<Wanda[cis]>
we were originally planning to do it by making pysim2 and scopes-lite, and thus obliterating the offending code wholesale, but since it just got reprioritized given the sim port situation, I'll just fix the existing code