05:07 <kc5tja> Hello; I have a design which I'd like to get estimated timing parameters from (in particular, maximum clock frequency).  I'm using Amaranth 0.4.3, and I tried installing amaranth_boards from GitHub (since the package in pypi is just a stub).  Where do I go from here though?  I'm looking at approximately 200 I/Os total, although I can stub a good

05:07 <kc5tja> number of those off if need be.  Any advice would be appreciated.  Many thanks in advance.

05:57 <kc5tja> When I attempt to create my own top.py file and run it, I get the following results:   https://gist.github.com/sam-falvo/f1a196eddf4188d079c5df256a6ae389

05:59 <whitequark[cis]> Amaranth 0.5 had a total rework of the memory subsystem, so it's very likely that if you upgrade to it you'll no longer hit this issue

05:59 <whitequark[cis]> it's not worth reporting because the 0.4 branch is no longer supported

05:59 <kc5tja> Ooh, I was unaware there is a new version out.  I'll update and try again.  Thanks!

06:52 <mabl[m]> Should you discuss it again, I like to throw in one more wrinkle:... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/HcqGYNLLZhXTdiqYQiiCZCJG>)

08:02 <kc5tja> Unfortunately, upgrading to 0.5 breaks my unit tests.  My register file code says that every read port returns zero, no matter what address I give.  I'll need to look further into this tomorrow or day after; it's way past my bed-time here.

08:11 <whitequark[cis]> <kc5tja> "Unfortunately, upgrading to 0...." <- you probably need to add the Memory as a submodule

11:48 <zyp[m]> <mabl[m]> "Should you discuss it again, I..." <- > <@mabl:matrix.org> Should you discuss it again, I like to throw in one more wrinkle:... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/LnUXZbqpWvsXyDdOJRZivZAy>)

11:49 <zyp[m]> when you have a 32-bit bus with granularity 8 bridged to an 8-bit CSR bus, you should drive csr_bus.w_stb once per enabled byte lane, like the wishbone bridge does here: https://github.com/amaranth-lang/amaranth-soc/blob/main/amaranth_soc/csr/wishbone.py#L94

11:51 <zyp[m]> so a 16-bit write arrives on the upstream bus as a 32-bit write with two enable bits set, you translate that to two independent 8-bit writes on the CSR bus, and a CSR register multiplexer further downstream takes care of reassembling those to a 16-bit write

12:02 <mabl[m]> Yes, I am doing this. I guess I was more talking about the memory layout. I was using [MemoryMap.add_resource](https://github.com/amaranth-lang/amaranth-soc/blob/main/amaranth_soc/memory.py#L314C9-L314C21) with alignment. That not only aligns the start but also the stop of the inserted range. It seems that the Mux then only sets the register element write strobe on [the aligned

12:02 <mabl[m]> stop](https://github.com/amaranth-lang/amaranth-soc/blob/main/amaranth_soc/csr/bus.py#L600).

12:02 <mabl[m]> So the 2times 8bit-write into the aligned 16bit wide register newer gets properly realigned until the stop address is written to. At least, that is how I understand all this. :-)

12:02 <mabl[m]> s/add_resource/add\_resource/, s///, s/realigned/reaassembled/

12:03 <mabl[m]> * Yes, I am doing this. I guess I was more talking about the memory layout. I was using [MemoryMap.add\_resource](https://github.com/amaranth-lang/amaranth-soc/blob/main/amaranth_soc/memory.py#L314C9-L314C21) with alignment. That not only aligns the start but also the stop of the inserted range. It seems that the Mux then only sets the register element write strobe on [the aligned

12:03 <mabl[m]> stop](https://github.com/amaranth-lang/amaranth-soc/blob/main/amaranth_soc/csr/bus.py#L600).

12:03 <mabl[m]> So the 2times 8bit-write into the aligned 16bit wide register newer gets properly reaassembled until the 32bit stop address is written to. At least, that is how I understand all this. :-)

12:11 <zyp[m]> oh, yeah, that looks correct

12:12 <zyp[m]> but in that case, the generated code would also treat it as a 32-bit register, issuing a write with all byte lanes enabled

13:18 <jfng[m]> <whitequark[cis]> "the right way to resolve this, I..." <- as this use-case seems to come up regularly (bridging a WB bus with an 8-bit granularity to a 32-bit CSR bus), i think it may be worthwhile to modify the CSR bridge as you just described

13:23 <jfng[m]> it already adds a clock cycle of latency, so aborting a transaction with ERR can be done here without adding more latency

15:20 <kc5tja> whitequark[cis] - that was it, thank you.  I was rushing to get things finished before the end of my vacation, and my eyes refused to see the obvious.  Thank you again.

15:59 <whitequark[cis]> no meeting today--I am feeling kind of unwell, apologies

16:00 <tpw_rules> sorry to hear that

16:01 <galibert[m]> Take care of yourself