11:12 <whitequark> <cr1901> "What I _actually_ want is "count..." <- cr1901: you could do that, but a more concise way is to use `count = Signal(data.Layout.of(self._view.data))`

11:15 <_whitenotifier-e> [amaranth-lang/amaranth] whitequark pushed 1 commit to rfc-issue-693 [+0/-0/±2] https://github.com/amaranth-lang/amaranth/compare/d99d443fe600...41924d1036e9

11:15 <_whitenotifier-e> [amaranth-lang/amaranth] whitequark 41924d1 - lib.data: cast ArrayLayout element shape before using width.

11:15 <_whitenotifier-e> [amaranth] whitequark synchronize pull request #697: Implement "Aggregate data structure library" RFC (#693) - https://github.com/amaranth-lang/amaranth/pull/697

20:49 <GenTooMan> any have examples of configuring a PLL? granted it's unlikely the same FPGA (ice40hx8k just because I have it) I'm just drawing a blank how to setup the PLL at this moment.

21:25 <d1b2> <dragonmux> give us a sec and we can share with you how to Instance() the PLLs - use icepll from the IceStorm tools to generate the settings to put into the Instance()

21:29 <d1b2> <dragonmux> https://gist.github.com/dragonmux/a71e0bddd36369895dbab274b118f6e3

21:30 <adamgreig[m]> I have a little ice40 example here too: https://github.com/adamgreig/amaranth-examples/blob/master/amaranth_examples/pll_ice40.py

21:30 <d1b2> <dragonmux> this particular instance uses the _PAD version which passes the pad through to the global fabric, but you can also use the _CORE version if you don't need that

21:31 <d1b2> <dragonmux> er.. sorry, uses the _2 version which passes through.. _PAD just means it's a PLL that consumes the pad, _CORE is for a PLL fed by the global clock fabric

21:33 <adamgreig[m]> and there's also _2F_CORE and _2F_PAD if you want to output two frequencies

21:34 <d1b2> <dragonmux> indeed, good shout

21:34 <adamgreig[m]> if you haven't found it already, the "Lattice ICE technology library" is a great reference, http://www.latticesemi.com/view_document?document_id=52046 I think

21:34 <adamgreig[m]> hmm

21:34 <d1b2> <dragonmux> we would second that

21:35 <adamgreig[m]> looks like there's a newer version at https://www.latticesemi.com/view_document?document_id=52206 but I think it's just fancier branding

21:35 <d1b2> <dragonmux> there are a couple of fixes, but nothing of consequence to the PLLs

21:36 <d1b2> <dragonmux> both are fine as a reference to the HX8K