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<clever___/D> so when it says 0x80 (128), it means /256
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<clever___/D> so if thats true, then take every x axis label, and halve them
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<clever___/D> so at 50mhz (displaying 100 in graph), i would expect 200mbit, and your getting 160mbit
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<clever___/D> given how linear it is, there seems to be an overhead somewhere in your code
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<clever___/D> but i'm not sure where
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<x2x6_/D> Ok, you are right about the mapping
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<x2x6_/D> I was printing out the divisor itself. It did not do the mess, I just did not bother. So now it really as you assumed could be just divisded by 2
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<x2x6_/D> Anyways, I think it's good progrees, so now the lower part of sdcard communication is tuned for max performance. Now need to check the surrounding code and PLLs
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<clever___/D> the PLL's shouldnt need any tuning, those just change the emmc reference clock input
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<x2x6_/D> I need to read the registers and dump a report at each boot what are the clock speeds