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21:05
<
f_ridge >
<x2x6_/D> Hi. Had too much work these days. Going to try again now.
21:42
<
f_ridge >
<x2x6_/D> Immediately as soon as I write to CMDTM register I get these values in interrupt register intr:00208001
21:43
<
f_ridge >
<x2x6_/D> bit 15 = ERROR, bit 21 DATA CRC ERROR..
21:43
<
f_ridge >
<x2x6_/D> thats immediately after I have done switch to 4 bit DAT, I will try to do it a bit earlier
21:44
<
f_ridge >
<clever___/D> is both the card and sdhci in 4bit mode?
21:44
<
f_ridge >
<x2x6_/D> Ahh, no
21:44
<
f_ridge >
<x2x6_/D> both are in 1 bit mode
21:44
<
f_ridge >
<clever___/D> i found that once i did the card in 4bit mode at the right time, all i got was crc errors, because the sdhost was still in 1bit mode
21:44
<
f_ridge >
<clever___/D> ah
21:44
<
f_ridge >
<x2x6_/D> in that case I'll try to turn it on first
21:46
<
f_ridge >
<x2x6_/D> No, same thing
21:47
<
f_ridge >
<x2x6_/D> As for Response RESP0: 00000900, STATUS REGISTER: 0x01ff0202
21:51
<
f_ridge >
<clever___/D> something i'm curious about, can you try reproducing some of my benchmarks?
21:52
<
f_ridge >
<clever___/D> in here, i'm stepping thru every possible clock divisor for the sdhost
21:52
<
f_ridge >
<clever___/D> and then reading 1mb from the card each time, and reporting the mbit rate
21:52
<
f_ridge >
<clever___/D> and i can clearly see its able to transfer 1 bit per clock, until it hits a wall at ~26mbit
21:53
<
f_ridge >
<x2x6_/D> What do you want me to run?
21:53
<
f_ridge >
<clever___/D> try doing a write benchmark, with different sdhci clock divisors
21:53
<
f_ridge >
<clever___/D> and see how the speed scales
21:56
<
f_ridge >
<x2x6_/D> Do you change clock divisors on the fly?
21:56
<
f_ridge >
<clever___/D> yep
21:56
<
f_ridge >
<GitHub Lines/D> ```c
21:56
<
f_ridge >
<GitHub Lines/D> for (int i=3; i<=70; i++) {
21:56
<
f_ridge >
<GitHub Lines/D> rpi_sdhost_set_clock(i);
21:57
<
f_ridge >
<GitHub Lines/D> uint32_t start = *REG32(ST_CLO);
21:57
<
f_ridge >
<GitHub Lines/D> bio_read_block(dev, buf, 0, (1024*1024)/512);
21:57
<
f_ridge >
<GitHub Lines/D> uint32_t stop = *REG32(ST_CLO);
21:57
<
f_ridge >
<GitHub Lines/D> uint32_t interval = stop - start;
21:57
<
f_ridge >
<GitHub Lines/D> float bits = 1024*1024*8;
21:57
<
f_ridge >
<GitHub Lines/D> float delta = interval;
21:57
<
f_ridge >
<GitHub Lines/D> double mbit = bits/delta;
21:57
<
f_ridge >
<GitHub Lines/D> printf("%f MHz, \t", ((double)vpu_clock)/i);
21:57
<
f_ridge >
<GitHub Lines/D> printf("%d uSec to read 1MB\t", interval);
21:57
<
f_ridge >
<GitHub Lines/D> printf("%f mbits/sec\n", mbit);
21:57
<
f_ridge >
<GitHub Lines/D> }
21:57
<
f_ridge >
<GitHub Lines/D> ```
21:57
<
f_ridge >
<clever___/D> this is how i did it
22:02
<
f_ridge >
<x2x6_/D> Ok, but I don't have sdhost. You mean that I used clock division on SDHCI or to compile lk-overlay and run on my sdcard?
22:03
<
f_ridge >
<x2x6_/D> I was thinking of doing your tricky PLL tweaks in undocumented registers, but I am not there yet
22:08
<
f_ridge >
<clever___/D> try doing the same things with your sdhci driver
22:08
<
f_ridge >
<clever___/D> at the divisors you have available
22:51
<
f_ridge >
<x2x6_/D> ok, running
22:51
<
f_ridge >
<x2x6_/D> I am using the mapped clock divs
22:51
<
f_ridge >
<x2x6_/D> results are pretty interesting
22:51
<
f_ridge >
<x2x6_/D> results are pretty interesting to watch(edited)
22:51
<
f_ridge >
<x2x6_/D> I am not going for graphs, I think it will not map to the same as yours
22:56
<
f_ridge >
<x2x6_/D> These are 1mb reads starting from the same sector
22:57
<
f_ridge >
<x2x6_/D> 101 while(1) {
22:57
<
f_ridge >
<x2x6_/D> 102 for (int i = 0; i < 7; ++i) {
22:57
<
f_ridge >
<x2x6_/D> 103 for (int j = 0; j < 20; ++j) {
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<
f_ridge >
<x2x6_/D> 104 struct blockdev_io io = {
22:58
<
f_ridge >
<x2x6_/D> 105 .dev = partition_dev,
22:58
<
f_ridge >
<x2x6_/D> 106 .is_write = false,
22:58
<
f_ridge >
<x2x6_/D> 107 .addr = buf_1mb,
22:58
<
f_ridge >
<x2x6_/D> 108 .start_sector = 0,
22:58
<
f_ridge >
<x2x6_/D> 109 .num_sectors = 1024 * 1024 / 512,
22:58
<
f_ridge >
<x2x6_/D> 110 .cb = NULL
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<
f_ridge >
<x2x6_/D> 111 };
22:58
<
f_ridge >
<x2x6_/D> 112
22:58
<
f_ridge >
<x2x6_/D> 113 bcm2835_emmc_set_clock(clocks[i]);
22:58
<
f_ridge >
<x2x6_/D> 114 blockdev_scheduler_run_io(&io, clocks[i]);
22:58
<
f_ridge >
<x2x6_/D> 115 }
22:58
<
f_ridge >
<x2x6_/D> 116 }
22:58
<
f_ridge >
<x2x6_/D> 117 continue;
22:58
<
f_ridge >
<x2x6_/D> The clocks part
22:58
<
f_ridge >
<x2x6_/D> 82 uint32_t clocks[] = {
22:59
<
f_ridge >
<x2x6_/D> 83 0x80,
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<
f_ridge >
<x2x6_/D> 84 0x40,
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<
f_ridge >
<x2x6_/D> 85 0x20,
22:59
<
f_ridge >
<x2x6_/D> 86 0x10,
22:59
<
f_ridge >
<x2x6_/D> 87 0x08,
22:59
<
f_ridge >
<x2x6_/D> 88 0x04,
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<
f_ridge >
<x2x6_/D> 89 0x02
22:59
<
f_ridge >
<x2x6_/D> 90 };
23:44
<
f_ridge >
<clever___/D> gotta run, work stuff, can read more when i finish