azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<tnt> ERROR: No wire found for port PACKAGE_PIN on destination cell misc_I.gps_pps_iob_I.
<tnt> What does that mean ? I don't remember seeing that one before ...
<tnt> nevermind ...
<tnt> (this was caused by using the same wire to normal logic and to a SB_IO.PACKAGE_PIN)
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