azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
<pie_>
oh hm thats an idea "Ultimately, qemu will be coupled with a system C or a verilog simulator to simulate the whole board functionalities." (looking at some old qemu repo, no idea if anything happened with this)
<pie_>
Which is to say, I wonder about what the status of qemu+verilog is. Does anyone know about any qemu/rtl simulation integration variants?
<pie_>
to provide proof of functionality and security. "
<pie_>
"To help address the current design complexity challenges, the Posh Open Source Hardware (POSH) program seeks to enable mathematically provable secure electronics and create an open source hardware IP ecosystem, along with accompanying validation tools. Under the program, researchers will work to develop methodologies, standards, and simulation as well as emulation technologies for the verification and mathematical inspection of analog and digital IP
<pie_>
https://github.com/aolofsson/POSH , ran into this repo by accident because apparently im not the only person that thought of combining xyce and qemu
<Forty-Bot>
the issue I see with qemu+verilog is mainly that qemu is fundamentally not cycle-accurate
<Forty-Bot>
for example, time continues on when mmio device drivers have callbacks
<Forty-Bot>
so if you have dev_read() which calls into your verilog simulation, the time will be different by the time it returns
<Forty-Bot>
it could be made to work, but all the existing models are very different from how verilog simulators typically work
<Forty-Bot>
renode is much more oriented towards this sort of thing