azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
<pie_>
Forty-Bot: I dont understand renode yet, but I think that's mainly for peripherals?
<pie_>
yeah, Im looking at qemu and how to try to meld jit with a cycle accurate simulator is not offhand obvious to me
<pie_>
IDK if it makes sense but my only idea so far is to have the jit translate everything to an emulated function that invokes verilator
<pie_>
but thanks for the input, what youre saying goes beyond that
<pie_>
Forty-Bot: do you know anyone I can talk to about working on this
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<Forty-Bot>
yeah, people have done verilator in renode for peripherals
<Forty-Bot>
for qemu there is a just a permeating attitude of "modern cpus are too complex to model (timing wise) so don't even try"
<Forty-Bot>
I think it is probably not worth it to work against the grain so to speak
<pie_>
Im fine if this ends up being just "research grade"
<pie_>
maybe simics would be a better fit but thats closed source i think (never used it)
<pie_>
I have low confidence in my abilities to execute on this but unless its really pointless I think this would be cool. (Im still willing to be talked down from it.)
<pie_>
jn: context above
<pie_>
Forty-Bot: I have two paragraphs typed up at this point with uncertainties, I think I should just say 1) "ok I want to try to use this for my toy cpu" and 2) can you elaborate on the timing issue
<pie_>
Im interested in the functional as opposed to the timing and performance side of things.
<pie_>
(other things would be neat, and planning ahead is important, but just this for starters...)
<pie_>
the starting point for all of this was "can I do something like swapping out (hypothetical) x86.c for mycrappycpu.v?"
<pie_>
Im not sure if that makes much sense unless I start implementing pci buses or who knows what though
<pie_>
I imagine the point is having usable peripherals and or development tooling; uart, storage, ..? - or just uart and loading images into ram directly.
<pie_>
It's questionable if Im better off than just integrating verilator into my own minimal framework.
<pie_>
(also planning to use haskell/clash down the line, and that just straight up compiles to executable code as well)