azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
lethalbit has quit [Ping timeout: 252 seconds]
Stary has quit [Ping timeout: 252 seconds]
helle has quit [Ping timeout: 252 seconds]
lethalbit has joined ##openfpga
helle has joined ##openfpga
Degi has quit [Ping timeout: 246 seconds]
Stary has joined ##openfpga
lethalbit has quit [Remote host closed the connection]
Degi has joined ##openfpga
lethalbit has joined ##openfpga
sgstair_ has joined ##openfpga
sgstair has quit [Ping timeout: 256 seconds]
<pie_>
afaict, good (introductory?) fpga review article from 2021 from Andrew Boutros and Vaughn Betz (dunno if these are known names, at least the former seems to be part of VTR which is mentioned in this article and i think may come up here, or maybe thats VPR); https://www.eecg.utoronto.ca/~vaughn/papers/casm2021_arch_survey.pdf
<pie_>
im noob
<pie_>
(though vpr seems to be a subset of vtr)
<pie_>
*review article on internal fpga architecture
<pie_>
about 6 pages in
<pie_>
*im about 6 pages in
<pie_>
argh.
<pie_>
have there been any significant developments since 2021?
<pie_>
when did fpgas stop using just pass transistors and start using buffers in routing?
<mwk>
that was a gradual process
<mwk>
on xilinx side, the first fully-buffered routing architecture was Virtex 2
<mwk>
the OG Virtex was partly buffered, in that length-1 interconnect was unbuffered, but length-2 and length-6 was buffered
<mwk>
earlier architectures also had *some* buffering sprinkled here and there, for long paths
sgstair_ has quit [Ping timeout: 256 seconds]
helle has quit [Changing host]
helle has joined ##openfpga
so-offishul has quit [Read error: Connection reset by peer]