azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<pie_>
somlo: thanks, ill take a look
<pie_>
did a little bit of searching on google scholar
<pie_>
given the closed nature of the tools i suppose you cant really audit the output before the bitstream? maybe you can get stuff to audit it if youre big enough?
<pie_>
or is this something people dont really care about
<pie_>
i was thinking if somehow crosstalk was a thing or something, messing with p&r output or such, would be harder to audit
<pie_>
(or i guess just meeting timing unreliably in certain places)