azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<markus-zzz> tnt, to report back on yesterdays suggestion to put the tri-state ctrl flops inside the io-cells I tried the following https://gist.github.com/markus-zzz/bb65d9484e16d38dee6f57f1fb070633
<markus-zzz> unfortunately my problem that the upper 8 data bits are occasional garbage remains.
<markus-zzz> of course if it actually works out as intended having all the interface flops in the io-cells is much than risking them ending up in fabric so it is a good change anyway.
<markus-zzz> I also had a quick look at the sdram pcb layout of the ulx3s and as far as I can see the traces for d[7:0] and d[15:8] are pretty symmetrical so I would expect there to be no major difference in delays. That is if I understood the suggestion correctly that the pcb would be the issue.
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