azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<sensille>
as i understand yosys currently does not support internal busses that are written in tri-state logic. would it be hard to add that?
<gatecat>
sensille: `tribuf -logic` should convert these into non-tristate logic, if that's what you're looking for?
<sensille>
probably, thanks for the pointer :)
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