azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
<Guest18>
Looking for some advice on how to examine the output of nextpnr. I am working
<Guest18>
on a SDRAM controller for ULX3S where I take care to instantiate BB,OB,OFS1P3BX
<Guest18>
and IFS1P3BX for all signals to make sure that (hopefully) the registers end up
<Guest18>
in the io-cells for consistent timing. Result is that things work fine as long
<Guest18>
as I only use half of the SDRAM data bus (the lower 8 bits), it passes hours of
<Guest18>
fibbonaci pattern verifications and it supports the rest of the soc booting
<Guest18>
linux. However when I try to use the full data bus the upper 8 bits contain
<Guest18>
occasional garbage. For both cases fibbonaci pattern verification in simulation
<Guest18>
using the Micron verilog model pass.
<Guest18>
Starting to suspect that things go wrong somewhere in the flow but I am not sure how I can examine the output to confirm this.
pbsds has joined ##openfpga
<whitequark>
IFS1P3BX is just the input flop, right?
<whitequark>
do you use a matching output flop?
<Guest18>
Yes, I have matching output flop for the BB (like data bus and dqm)
<Guest18>
(and all the other signals that are just output)
<tnt>
Do you also use IO FF for tristate control ?
<tnt>
Also you the two halves might need different clock phase depending on the hw.
<Guest18>
tnt, that is a thing that I have actually thought about that I do not use a IO FF for tristate control. Not sure how to do it, would that just be another OFS1P3BX or what would I instantiate? Again I guess it boils down to how would I verify the results.
<Guest18>
For different clk phase for lower/upper you mean I should check the trace lengths on the board?
<tnt>
yeah it's OFS1P3BX as well AFAIR.
<tnt>
I don't think there is really any way to "verify" anything ...
<tnt>
you can check the .json file but that will just show you what you instanciated.
<tnt>
I'm not even sure the nextpnr gui mode for ECP5 shows any detail of the fina config of the IO pads.
<Guest18>
ah, and then I would have one of these for each one bit tristate buffer?
<tnt>
yes.
<Guest18>
makes sense. I will try this and report back (may not be until tomorrow). Thank you!