azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<Degi>
agg: Maybe you can try increasing the clock beyond design limits too
<agg>
I guess that would increase power use pretty linearly but it also shifts the frequency the decoupling has to deal with?
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