02:24 <azonenberg> florolf: so i checked on the sim. I modeled one single ended line from the board slightly simplified in geometry but same stackup/length/dimensions

02:25 <azonenberg> https://www.antikernel.net/temp/10g-s11.png is S11, there's a small artifact around 11 GHz causing a spike (probably sim box resonance) that I could work on fixing if i really cared but this is just a quick sim

02:25 <azonenberg> https://www.antikernel.net/temp/10g-eye1.png and here's a PRBS-31 simulated through the channel

02:25 <azonenberg> it's not a perfect match but it's pretty decent. This doesn't account for connector launch mismatch which is probably the biggest thing degrading the signal

02:27 <azonenberg> If you ignore the artifacts from the box resonance it's a nice smooth rolloff to about -1.5 dB insertion loss at 16 GHz. This is optimistic as the real board is ENIG plated and you get loss due to the nickel plating

02:27 <azonenberg> Which I could simulate, but didn't for this quick demo

11:44 <florolf> azonenberg: okay, interesting. i need to check the calculations later. would you mind sharing the .son?

12:27 <azonenberg> florolf: https://www.antikernel.net/temp/sfp-cpwg-single-mergedvias-cropped.zon here's the .zon which is a packed archive of the project plus analysis results

12:27 <azonenberg> it's a simplified geometry since the real thing would have used like 50GB of RAM to sim at useful resolution

12:27 <azonenberg> but i kept the stackup, trace/space dimensions, and overall trace length the same

12:35 <azonenberg> I have a sim running on the full geometry that i just kicked off but it might take a while

12:38 <azonenberg> It's 75,730 mesh cells and uses 44GB of RAM to simulate :p

13:28 <Peanut> Howdy - I'm looking for some information on how to use the DCU (SERDES) on the ECP5, I haven't been able to find much documentation. I'd like to use it to drive an SFP interface, and either use the PCS (8b/10b) or implement my own to do comma alignment.