azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<florolf>
or i guess i can just drop it into oshpark directly. any known problems with the design?
<azonenberg>
florolf: I may have a few spares, i ordered 3 from oshpark and only populated one
<azonenberg>
but yeah probably easioest to just order it
<azonenberg>
It works fine, i use it all the time
<azonenberg>
glscopeclient has a working 10gbase-r protocol decode
<florolf>
ok great. yeah, we've been using glscopeclient
<azonenberg>
With what scope, out of curiosity?
<florolf>
tek MSO64
<azonenberg>
(also if you're not in #scopehal yet you probably should be?)
<azonenberg>
ah yeah. It works with the mso6 but performance is not the greatest in my experience
<azonenberg>
LeCroy stuff is generally faster
<azonenberg>
i tried to work with some tek FAEs to imporve performance
<azonenberg>
but then the loaner scope i was using disappeared
<azonenberg>
and i never got access to another to debug
<florolf>
azonenberg: you've said that before :) i've just never updated my irc client config apparently
<azonenberg>
Anyway, yeah decoding 10GbE is straightforward
<azonenberg>
CDR PLL, threshold, 64/66b, then 10gbase-r on the 64b66b
<azonenberg>
The raw 64/66 decode outputs frames color coded for data or control and shows you the raw 64-bit hex code word
<azonenberg>
then the 10gbase-r decode converts that to ethernet frames
<azonenberg>
Also BTW i'm hoping to get a litescope driver for libscopehal at some point if you are interested
<azonenberg>
This is a great example of the kind of use cases i had in mind
<azonenberg>
combining on-FPGA digital and external analog captures into a single coherent debug view of the system
<azonenberg>
The integration isn't there yet but that's the endgame
<azonenberg>
As far as the fixture goes, it takes two SFP+ optics obviously
<azonenberg>
RX of each SFP+ is fed through two single ended 50 ohm resistive splitters
<azonenberg>
one leg of the splitter goes to TX of the other
<azonenberg>
the other leg goes to the SMAs
<azonenberg>
The splitters are standard 6 dB ish resistive splitters which do not have good isolation. What this means is, if you are NOT using one of the probe ports, it must be terminated
<azonenberg>
otherwise you get fairly strong reflections back into the TX path
<azonenberg>
Won't break anything but will play hell with your BER
<azonenberg>
By default you should have jumpers on LOS, FLT, SDA, and SCL to provide pullups on those signals
<azonenberg>
As well as on the left (1) position for RS0 and RS1
<azonenberg>
The I2C buses are brought out to a 5 pin header you can hook up to to query the eeproms or DOM
<azonenberg>
The barrel jack is 3.3V center positive, i should have labeled it
<azonenberg>
it's unregulated and goes direct to the SFPs after some noise filtering
<azonenberg>
so you want a fairly accurate 3.3
<florolf>
i just had the schematic open and was pondering adding a regulator
<azonenberg>
And yeah this fixture works well for 10G. It can definitely be improved, i dont think i added ground plane cutouts under the SMA center pins for example so there is likely a bit of reflection