whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Adrien[m]> vancz: yes, I've implemented my own operators netlist-level for Xilinx 7-series FPGAs, for specific purposes, mainly low quantization
<tpb> Title: Adrien Prost-Boucle / hwopt-xilinx-7series · GitLab (at gricad-gitlab.univ-grenoble-alpes.fr)
<Adrien[m]> Example with a 7-input ternary adder block, wth direct instantiation of LUTs and CARRY, the synthesis tools do recognize the primitives and don't touch these implems, that is convenient.
<tpb> Title: hdl/adder_7in_ter.vhd · main · Adrien Prost-Boucle / hwopt-xilinx-7series · GitLab (at gricad-gitlab.univ-grenoble-alpes.fr)
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<vancz> cool
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