MyNetAz has quit [Write error: Connection reset by peer]
kristianpaul has joined #yosys
Wolfvak has joined #yosys
_catircservices has joined #yosys
srk has joined #yosys
anuejn_ has joined #yosys
vup has joined #yosys
adamgreig has joined #yosys
cyrozap has joined #yosys
jix has joined #yosys
jn has joined #yosys
m42uko has joined #yosys
marex has joined #yosys
ZipCPU has joined #yosys
xutaxkamay has joined #yosys
Psentee has joined #yosys
tmiw has joined #yosys
gatecat has joined #yosys
flokli has joined #yosys
juri_ has joined #yosys
buhman has joined #yosys
bjonnh has joined #yosys
gruetzkopf has joined #yosys
esden has joined #yosys
DX-MON has joined #yosys
sorear has joined #yosys
mithro has joined #yosys
MoeIcenowy has joined #yosys
Raito_Bezarius has joined #yosys
mwk has joined #yosys
mobius has joined #yosys
striving has joined #yosys
unkraut has joined #yosys
Raito_Bezarius has quit [Max SendQ exceeded]
Raito_Bezarius has joined #yosys
Guest1880 has joined #yosys
Semisol[m] has joined #yosys
flag has joined #yosys
Zaba has joined #yosys
chipb has joined #yosys
dxld has joined #yosys
sugarbeet has joined #yosys
DoubleJ has joined #yosys
knielsen has joined #yosys
edm has joined #yosys
MyNetAz has joined #yosys
mrec has quit [Remote host closed the connection]
FabM has joined #yosys
FabM has quit [Changing host]
FabM has joined #yosys
krispaul has joined #yosys
kristianpaul has quit [Ping timeout: 248 seconds]
lxsameer has joined #yosys
lxsameer has quit [Ping timeout: 245 seconds]
lxsameer has joined #yosys
Adrien[m] has joined #yosys
<Adrien[m]>
Hi ! I'm trying to synthesize a verilog component with yosys, for xilinx target. But I'm hitting a issue related to some defparam but there are nodefparam in the design... Is there any known issue about that in yosys ?
<Adrien[m]>
ZipCPU: it is your component `aximm2s`, looks very promising to experiment with hardware acceleration on Zynq :-)
<ZipCPU>
(Judging from your .tar.gz file, that's what you already have ...)
<ZipCPU>
I can't comment on whatever ghdl is up to (don't have the most recent version installed here ...), but yosys seems to have no problems with aximm2s on down--save one: you also need the sfifo.v file from wb2axip.
<Adrien[m]>
I provided the ghdl-generated verilog in the archive to ease reproducing the issue. I'll add sfifo.v and try again.
<ZipCPU>
Sorry, I just don't do much with VHDL, so I can't reproduce that part of your issue.
<Adrien[m]>
No improvement with sfifo.v added : Yosys is still complaining. I'm now using a freshly-compiled yosys. If the version you are using is older then I'm probably hitting a regression.
<ZipCPU>
Could be, but remember I'm also running from aximm2s.v on down, without touching the VHDL files.
<Adrien[m]>
What is most weird is that there is no defparam anywhere, even in the ghdl-generated code. That generated code is the simplest form of verilog imaginable so it's very easy to scan for dubious generate code - I found nothing...
hwpplayer1 has quit [Ping timeout: 252 seconds]
<ZipCPU>
Try this: Set the parameters of aximm2s explicitly, rather than overriding them. Remove the "generic" portion of the component declaration. See if that helps.
<Adrien[m]>
I think I have found the root cause, in the instantiation of aximm2s. Indeed coming from vhdl eases triggering that issue. Two parameters are (erroneously) set here, because they provide the size of some ports. But these are localparams in the aximm2s implementation, so setting these externally is forbidden, and the error message is misleading.
<ZipCPU>
o/
<ZipCPU>
It would certainly be a Verilog error to try to override a localparam.
<Adrien[m]>
You did guide me in the right direction. Thanks !
<ZipCPU>
You did all the work. Still, I'm glad I could help.
<Adrien[m]>
So we will use a slightly edited aximm2s to continue our experiments : convert these 2 localparams to parameters, so they can be declared in vhdl side, and be referenced in port declarations. That'll do for now.
<Adrien[m]>
I've got a real question for you, though : have you already worked with Zynq-7000 SoC ? It uses AXI3. So initially we thought to experiment with axi32axi and axi3axi3 but comments indicate these are not really finished or validated.
<Adrien[m]>
So I thought we could try modified aximm2s and axis2mm to just cap the burst length to 16, the rest should be compatible. Are there reasons to believe this may not work ?
flag has quit [Ping timeout: 246 seconds]
flag has joined #yosys
<ZipCPU>
Adrien[m]: That's pretty close to what you might need to do.
<ZipCPU>
The issue with conversion from AXI4 to AXI3 is that ... I haven't gotten the logic working (yet) to convert bursts to smaller burst sizes.
<ZipCPU>
However, if you just limit the burst size to 16 beats you are then over halfway there.
<ZipCPU>
You'll also want to set both bits of AxLOCK to zero. (AXI3 has a two bit AxLOCK value) You're likely to want to double check the AxCACHE bits.
<ZipCPU>
Oh, and you'll need to set WID to the AX_ID used by the MM2S controller.
<ZipCPU>
Those should be all the updates you need.
<ZipCPU>
(Why AxCACHE? Because the meaning of that bit-field changed between AXI3 and AXI4 as I recall.)
lxsameer has quit [Ping timeout: 276 seconds]
hwpplayer1 has joined #yosys
orhosko has joined #yosys
<orhosko>
hello everyone,
<orhosko>
I'm trying to create a byte/halfword/word addressable bsram for tangnano20k. I both tried 32 bit memory and 8 bit one. 32 bit one fails when addr%4==1 etc. since it requires to access more than 1 word at the same time. And 8 bit based cannot be synthesized I'm not sure why. Do you have any ideas or some example. Or is it just not possible?
<orhosko>
Here is my code if it helps:
<orhosko>
```
<orhosko>
(* ram_style = "block" *) // errors if not possible
<orhosko>
logic [7:0] mem[2**12]; // 4KB example
<orhosko>
logic [3:0] write_enable;
<orhosko>
always_comb begin
<orhosko>
case (fn3)
<orhosko>
`FN3_SB: write_enable = 4'b0001;
<orhosko>
`FN3_SH: write_enable = 4'b0011;
<orhosko>
`FN3_SW: write_enable = 4'b1111;
<orhosko>
default: write_enable = 4'b0000;
<orhosko>
endcase
<orhosko>
end
<orhosko>
logic [31:0] rdata;
<orhosko>
integer i;
<orhosko>
always @(negedge clk) begin
<orhosko>
I broke the for part while pasting. It should be
<orhosko>
```
<orhosko>
always @(negedge wclk) begin
<orhosko>
rdata <= 0;
<orhosko>
for (i = 0; i < 4; i = i + 1) begin
<orhosko>
if (write_enable[i] && wr_en) mem[_addr_in+i] <= data_in[8*i+:8];
<orhosko>
rdata[8*i+:8] <= mem[_addr_in+i];
<orhosko>
end
<orhosko>
end
<orhosko>
```
<janrinze>
orhosko: do you really want negedge there?
<orhosko>
janrinze: all the other part uses posedge, it is single cycle core and it is working in a simulation only that way. Is it that bad a thing?:/
<janrinze>
orhosko: why not double the frequency and have it a dual cycle CPU?
<orhosko>
If this is not possible it will be the only solution i guess
<janrinze>
anyway, it seems like you are making it way more complicated than it is. You probably want to do byte access, halfword access and word access.
<janrinze>
byte access usually allows for all sequential bytes, not just the bottom byte of the 32 bit word.
<janrinze>
Do you only want to access the bottom byte?
<orhosko>
isn't this byte address, I'm not sure how can i simplify
<janrinze>
well your example writes to a bottom byte, bottom half word or a word. Right?
<janrinze>
Ah.. you are trying to have a byte wide memory to do 4 writes in one go with word writes!
<orhosko>
I don't think so word size 32 but I use byte addressing.
<orhosko>
yes exactly
<janrinze>
that requires 4 write ports to the same memory.
<orhosko>
so being not synthesizable was correct
lxsameer has joined #yosys
<orhosko>
if I made it 32 bit wide it would still require 2 write ports right? not correctly alligned writes would access 2 words
<orhosko>
and i believe it would require more logic
<janrinze>
yes that could work.
<orhosko>
I'm not sure whether 2 write ports is allowed though
<janrinze>
you can have true dual-port RAM that allows 2 ports
<janrinze>
so that will work.
<janrinze>
is the CPU your own design or has it a known ISA?
<orhosko>
it is riscv i should have mentioned that too...
<orhosko>
is there a good resource that you know
<orhosko>
is true dual-port RAM supports 2 write + 1 read. That would be 3 ports.
<janrinze>
RISC-V can do byte access.. just use the proper write flags from the RISC-V
<janrinze>
read/write can be done on one port
<orhosko>
im not sure what would be the proper flags.
<janrinze>
true dual-port can do read and write on port 1 , read and write on port2
<orhosko>
>read/write can be done on one port
<orhosko>
then still i cannot write a word to not word alligned address. I am not sure if it is required in the specification. If not this will be the best solution for my case ig.
<janrinze>
normally there is are 4 byte select bits. the CPU will choose which bytes from the 32 bit word are written to.
<orhosko>
i didn't understand:(
<janrinze>
I don't know if RISC-V actually allows non-word aligned word-access. Most CPUs would read 2 words sequentially and then shift it to align.
<janrinze>
a 32 bit bus to memory would have 4 signals to let the memory know which byte will be written to.
<orhosko>
ok it make sense. a quick search says it is not mandatory to support non-word aligned word-access.