whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<vancz> Can I read somewhere about what kind of techniques are used to compile verilog to rtl? Specifically the uh...layer that implements whatever it is that is done to match the "procedural" verilog code to synthesized primizives?
<vancz> primitives
<vancz> In general, to satisfy my curiosity.
<vancz> (and how this results in unintuitive synthesis insanity)
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<whitequark[cis]> basically every vendor does their own thi g
<whitequark[cis]> s/thi g/thing/
<whitequark[cis]> what yosys does is kind of some of the worst implementations I think
<whitequark[cis]> just look at the recently filed memory init issue
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