whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<xiretza[cis]> I need to do some clock gating crimes on iCE40, does anyone have resources on switching characteristics of LUT4s?
<xiretza[cis]> I need to gate a nonperiodic clock input (really a counter event input) with an async gate signal, which is doable enough with discrete gates that have well-defined output transition characteristics, but I don't know how LUT4s behave.
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<whitequark[cis]> they're reasonably well behaved IME
<whitequark[cis]> i think you probably want to use the MSB input with yosys since that one controls the last mux
<whitequark[cis]> but check the specify block
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