whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<famubu[m]> Any idea what I can try tweaking to get it right? I suppose it would be the constraints file?
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<famubu[m]> Well.. found at least one place where I goofed up.
<famubu[m]> The constraint file treated a 21-bit vector as a single bit.
<famubu[m]> So I modified to make 21 seperate mappings to pins: https://bpa.st/AZNQ
<tpb> Title: View paste AZNQ (at bpa.st)
<famubu[m]> I am not sure if all those pins are available to use as general IO.
<famubu[m]> Also tried gowin eda. That too is saying that frequency cannot be found.
<famubu[m]> Gowin eda tool said: 'No timing paths to get frequency of clk!'
<chipb> do you need to annotate your clock like https://github.com/YosysHQ/yosys/blob/main/examples/gowin/demo.sdc or something?
<chipb> I don’t know yosys, but “Info: Cell inp not found” seems a bit concerning to me.
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