whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<cr1901> Does anyone have an example of using yosys w/ xilinx and then throwing it into vivado (perhaps skipping its synth step and going straight to pnr or the opt_design part)?
<cr1901> throwing it == throwing the yosys synthesized design of Xilinx prims
<cr1901> Also, question for future-me to answer: why does "yosys foo.v" do an implicit "read_verilog -defer", but "yosys -f verilog foo.v" does not?
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<whitequark[cis]> because of legacy code and questionable choices
<whitequark[cis]> it's an entire rabbit hole
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<cr1901> Okay well, I was testing something with setattr using a script, and I put my source files on the CLI. Unless I did -f verilog explicitly, the setattr selections wouldn't select anything, and that's how I found out about the -defer option.
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