<cr1901>
Okay, I have more than one design w/ this issue... seems that "synth_lattice -family ecp5" isn't parsing mem_v2 cells correctly when read from a file.
<cr1901>
^Ignore the above... works with synth_ecp5, doesn't work with synth_lattice -family ecp5. So whatever the difference between the two when hier -check runs is the problem
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<tnt>
Is it ok to add "vendor primitives" that the vendor doesn't support ? I'd like to add a `SB_PLL40_2_CORE` primitive ... It's a mix between SB_PLL40_2F_CORE and SB_PLL40_2_PAD where the clock used for the PLL is from REFERENCECLK but whatever is on the PAD of the PLL is independently passed to output A of the PLL ...
<tnt>
Something you can't do with the vendor tools but from testing this morning hacking the bitstreams config, you can actually do in hardware.
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<chipb>
not a yosys developer, but I'd suggest that caveat should be very well marked at least. there's any number of reasons the vendor doesn't expose the feature, not all of which involve them trying to slip a hardware easter egg by their hapless users.