whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Guest42> Hi, I have some problems about the sat pass in yosys
<Guest42> Does sat support set two signal not equal? For example there are two registers : reg [3:0] a, a1; how can I constraint a != a1?
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<mewt> 10;rgb:9700/9d00/b40011;rgb:2000/2700/460025
<mewt> sorry
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<hm> Hi everyone, I asked a question about using the 'sat' pass in Yosys for parsing Verilog files a couple of hours ago. I would really appreciate it if anyone with experience could offer some guidance. Thanks in advance for your help!
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