<azonenberg>
Sooo avnet canceled my stm32f777 order because it was "fullfilled by newark" and newark didn't have it in stock
<azonenberg>
well duh, i was placing a backorder
<azonenberg>
i expected them to ship when newark *did* have it
<azonenberg>
Anyway, i placed a new order directly with newark which is correctly listed as a backorder for six stm32f777nih6's
<azonenberg>
(was gonna get five but six gets me free shipping)
<azonenberg>
current expected ship date is mid July which isn't great but... it still beats digikey not giving an ETA
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<d1b2>
<Uwe> I have TPS60403 pending at Farnell, a Avnet daughter and already had about ten mails with shift in estimated delivery. Good Luck!
<azonenberg>
Since the chip crisis hit, i've had one backorder actually ship, three xc7s15's that came in a month or so ago. everything else i bought was in stock
<azonenberg>
or is still pending
<azonenberg>
the next scheduled ship is a single xc7a200t-1ffg1156 which was originally eta dec 1st and just slipped to the 8th
<azonenberg>
that sounds more like shipping than production delays so fingers crossed it comes soonish
<azonenberg>
but i'm not in a huge rush on that, as i don't have any of the other parts that will go on that board yet
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<azonenberg>
Aaand they just bumped it to the 15th
<azonenberg>
lovely
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<someone-else>
I wonder what % of parts will be discontinued before shortages are resolved..
<azonenberg>
someone-else: sooo guess what i just realized?
<azonenberg>
I *can* use the XCKU025 for VOLLUM, the 1+ GHz scope using the full rate AD9213
<azonenberg>
I had previously neglected it, because it only has 12 GTH lanes. And I need all 12 for talking to the ADC, leaving none to talk to the backplane
<azonenberg>
That was before I realized I was being stupid
<azonenberg>
yes, i need twelve transcievers to talk to the ADC
<azonenberg>
Yes, I need one or more to talk to the backplane
<azonenberg>
But those are all unidirectional links
<someone-else>
yep
<azonenberg>
So i can have 11 be RX-only and one be bidirectional, except the RX is coming from the ADC and the TX is going to the backplane
<someone-else>
can have a 12-lane backplane even
<someone-else>
there's no reason to, of course
<azonenberg>
I was actually thinking i'd have a 2 lane backplane because the backplane has transceiver capacity limits too
<azonenberg>
the backplane could have 7k160t in ffg676
<azonenberg>
actually that would need 1 backplane lane max still
<azonenberg>
you could have up to 7 channel cards and one 10G link to the outside world, or 4 channel cards and a 40G link
<someone-else>
sounds cool
<someone-else>
would AD9213 be outputting 10gbps per lane? I think that's what's required for 6GSPS
<azonenberg>
Correct
<azonenberg>
12.5 actually
<azonenberg>
10 gbps data 8b10b
<azonenberg>
The xcku025 has 208 HP I/O pins which is enough for a single DDR4 SODIMM
<azonenberg>
Any speed grade of KU+ is sufficient to do 12.5 Gbps on the GTHs
<someone-else>
hmm, my calc shows 8gbps*12 lanes at 6gsps@16bits output
<azonenberg>
no
<someone-else>
(10gbps with 8b10b)
<azonenberg>
you're thinking two different scopes
<azonenberg>
ZENNECK will be 7a200t-1ffg1156c per channel, 6 Gsps AD9213 downclocked to 5 Gsps to fit in the 6.25 Gbps GTP switching limit
<azonenberg>
VOLLUM will use the 10 Gsps speed grade of the AD9213
<someone-else>
ah, right
<azonenberg>
and an ultrascale FPGA
<azonenberg>
12 lanes * 10 Gbps = 120 Gbps data we need to buffer in RAM, and 12x 12.5 Gbps transceivers
<azonenberg>
So assuming we used a -1 ku025, our max ddr4 speed is 2133 MT/s
<azonenberg>
64 bits * 2133 is 136 Gbps of DDR bandwidth, which is a bit tight for writing 120 Gbps to
<azonenberg>
actually wait a minute i'm misreading the datasheet
<azonenberg>
it can only do 2133 in -1 for a single rank component
<azonenberg>
DIMMs top out at 1866, to get 2133 you need -2
<azonenberg>
So the ku025 is not going to work
<azonenberg>
We'd need to bump up to something like the KU035 in FBVA900, which has 364 HP pins - enough for dual channel DDR4 1866 in -1 or 2133 in -2/-3
<azonenberg>
assuming single rank dimm
<azonenberg>
2x 64 bit memory channels @ 1866 MT/s is 238 Gbps of bandwidth, which should be more than adequate for 120 Gbps of streaming writes
<someone-else>
do you account for ad9213 overhead bits when calculating the jesd204 bandwidth? didn't read the datasheet, but some jesd adcs only support using something like 16bits per sample
<azonenberg>
My understanding is that the ad9213 can run at 12 bit per sample mode
<someone-else>
having two dimms can make the design easier overall since they can run at lower speed
<azonenberg>
Yeah
<azonenberg>
I was thinking i'd run them at 1600 to buy some timing margin
<azonenberg>
but the fpga and memory would be 1866 capable
<azonenberg>
in any case, ZENNECK comes first
<azonenberg>
anyway, table 26
<azonenberg>
N=12
<azonenberg>
1 virtual converter, line rate = 1.25*Fout, L=12
<someone-else>
I see, cool
<azonenberg>
do you agree that's the config i'd want to use there?
<someone-else>
I'd check IO assignments with MIG first, theoretically there might be some surprises with required ddr assignments
<someone-else>
overall seems good
<someone-else>
if I was using ad9213 I might've also considered using two $50 kintexes per adc (each with its own dimm) instead :-)
<azonenberg>
you mean with half the jesd204 into each one? The problem with doing that is triggering. I need full resolution ADC data in one FPGA in order to be able to do level triggering with full 12 bit resolution
<azonenberg>
also since i'm not buying from china i don't have $50 kintexes :p
<someone-else>
two fpgas could in principle OR their trigger signals (each from half of adc bits)
<someone-else>
or do the same thing on full 12bit sequential samples since it's probably how bits are packed into the jesd links
<someone-else>
mythical $50 kintexes can probably soon be replaced with properly supplied CertusPro-NXes
<someone-else>
I think they will be $100 or less
<someone-else>
although, considering the adc cost this might be moot
<electronic_eel>
someone-else: if you don't have the full adc data in one fpga you rule out stuff like deembedding the probe before trigger (see the chat from some days before)
<someone-else>
true
<someone-else>
though trigger can potentially be (re)processed/filtered offline later since it doesn't have to be realtime
<someone-else>
one fpga per adc is easier for sure
<azonenberg>
And yes, i also want to be able to do realtime de-embeds down the road
<azonenberg>
To flatten both probe *and* trigger response
<azonenberg>
and frontend*
<azonenberg>
Just bought a $238 ebay'd Dx20-SI probe tip (MSRP $860). I wanted a sacrificial wavelink tip i could abuse a bit and run some tests on, as well as stealing parts off of to evaluate against my own designs
<azonenberg>
so even if it's somewhat damaged it should still be mostly usable for what i want
<azonenberg>
It was listed as "for parts" but emailing with the seller they say it's fully working and was listed as "parts" because it wasn't a complete probe
<azonenberg>
which i was fine with, it kept the price down :p
<someone-else>
azonenberg: ebay one has black tip resistors, not the white ceramic ones discussed earlier
<someone-else>
wonder what these are
<someone-else>
anybody has 100gbe PRBS waveforms? wanna debug mine, look kinda bad (eye closed) via a solder-in probe
<someone-else>
12.5gbps and below look fine, but 25gbps aren't
<someone-else>
wonder how bad 25gbps ones look when acquired with a real scope, preferably via a probe (not 50ohm coax)
<azonenberg>
I have some FPGAs and ASICs with 28G SERDES on them that I can get PRBS's off
<azonenberg>
But I only have a 16 GHz scope and 13 GHz probes right now
<azonenberg>
so they won't look great
<someone-else>
sure they won't be stellar, but I think eye still should be reasonably open with 13ghz bw
<azonenberg>
(I'm also not even sure my CDR can lock to a 28 Gbps signal with 40 Gsps sample rate)
<azonenberg>
If you can hold on a few months I plan to pick up some 16 and/or 25 GHz diff probes, and upgrade the scope to 80 Gsps interleaved capability
<someone-else>
no rush
<someone-else>
though i'll probably get to the bottom of this sooner
<someone-else>
measuring the prbs source I'm using via 50ohm cables will probably be enough to know where the problem is
<someone-else>
the board I'm measuring this on (one of the MS catapult accelerators) is actually 40gbe, so might be board's SI combined with the probe response/loading
<someone-else>
(prbs is generated by ds250df810 and the probing point is pretty close to it)