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<re_irc> <@j​amesmunns:m​> I can kinda see it
<re_irc> <@j​amesmunns:m​> as_mut you have to convert then match
<re_irc> <@j​amesmunns:m​> iterating just does something zero or one times
<re_irc> <@j​amesmunns:m​> how significant is the diff?
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<re_irc> <@x​obs:m​> Hi, I've got an embedded Rust question: How can I ensure a type is aligned? Alternately, how can I troubleshoot a type not being aligned? I'm running into an issue on RISCV-32 where `u64` claims `align_of()` is 8, but it's getting allocated at e.g. `0x8001ff5c`. Rust doesn't like me placing `#[align(8)]` over it.
<re_irc> <@x​obs:m​> I did manage to get it to align by sticking it in a newtype that had `#[align(32)]` over it. Any smaller numbers wouldn't work.
<re_irc> <@x​obs:m​> Do `u64` values align properly on ARM? Is it just a riscv32i thing? Do `u64` align properly for any other riscv32i users?
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<re_irc> <@w​illeml:m​> firefrommoonlight: rfuest got qpi erase/write working
<re_irc> <@f​irefrommoonlight:m​> Awesome! Going to try that later this week
<re_irc> <@f​irefrommoonlight:m​> And going to compare it to what I've written
<re_irc> <@w​illeml:m​> How would I go about implementing flash algorithm or something so that dfu-util and probe-rs can flash stuff onto the QPI external flash?
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<re_irc> <@d​isasm-ewg:m​> xobs: I checked with two global statics (one to shift the other) and 64-bit value allocates at the correct address. rustc 1.53.0
<re_irc> <@d​isasm-ewg:m​> What allocates the variable at `0x8001ff5c` in your case?
<re_irc> <@x​obs:m​> disasm: it's stack-allocated.
<re_irc> <@x​obs:m​> ```rust
<re_irc> <@x​obs:m​> println!("Alignment of u64: {}", core::mem::align_of::<u64>());
<re_irc> <@x​obs:m​> let single_u64 = 443u64;
<re_irc> <@x​obs:m​> pub fn alignment_check() {
<re_irc> <@d​isasm-ewg:m​> xobs: Hmm, you know what. Maybe sp is not 16-byte from the very begginning
<re_irc> <@x​obs:m​> That's a very good thought.
<re_irc> <@x​obs:m​> Let me see if that fixes things.
<re_irc> <@d​isasm-ewg:m​> I've never thought about this for riscv, so maybe it's also a problem in riscv-rt
<re_irc> <@d​isasm-ewg:m​> Anyway, I can't reproduce this on godbolt, and it's clearly seen that sp is modified in 16-byte increments and in all my tests the 64-bit variable is properly aligned assuming sp is 16-byte aligned
<re_irc> <@x​obs:m​> Good call about it being in `riscv-rt`. Let me modify the stack to ensure it's 16-byte aligned. Do you think `riscv-rt` will have a similar issue, then?
<re_irc> <@d​isasm-ewg:m​> xobs: At least there is no explicit alignment in riscv-rt, it should be added. But looking at the code, I think sp should be aligned in most cases.
<re_irc> <@w​illeml:m​> is now alloc free!
<re_irc> <@d​isasm-ewg:m​> xobs: sp misalignment would also explain why it doesn't work for values less than 32
<re_irc> <@x​obs:m​> disasm: That's a very good point. I've gone back and ensured that `sp` is 16-byte aligned, and it does seem to be working now. Thank you for pointing that out.
<re_irc> <@d​isasm-ewg:m​> Wow, great!
<re_irc> <@x​obs:m​> I guess I didn't realize that was one of the assumptions that is made about stack is that it's aligned that way.
<re_irc> <@x​obs:m​> I thought `"e-m:e-p:32:32-i64:64-n32-S128"` indicated that it needed to be 32-bit aligned. My mistake for mis-decoding that.
<re_irc> <@d​isasm-ewg:m​> Yeah, I also forgot about this and recalled when I saw a godbolt assembly output
<re_irc> <@d​isasm-ewg:m​> I created an issue in riscv-rt
<re_irc> <@x​obs:m​> Thanks. And amazing detective work.
<re_irc> <@w​illeml:m​> Does anyone know the name of the library that provides flashAlgo traits?
<re_irc> <@d​isasm-ewg:m​> willeml: flash-embedded-hal?
<re_irc> <@w​illeml:m​> No, it's something different
<re_irc> <@d​isasm-ewg:m​> spi-flash?
<re_irc> <@w​illeml:m​> I am pretty sure it's not that, flashAlgo is to let you flash external flash chips from a computer
<re_irc> <@d​isasm-ewg:m​> spi-memory seems to have this
<re_irc> <@w​illeml:m​> Is there an easy way to seach for a crate containing a trait with a specific name? I had found the crate a while ago, but forgot the name of the crate... Even though I remember the name of the trait
<re_irc> <@d​isasm-ewg:m​> You can try searching Github with the trait name in double-quotes
<re_irc> <@w​illeml:m​> I wonder if is it, I thought I saw it on, but maybe not, anyways, thanks!
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<re_irc> <@t​iwalun:m​> The probe-rs flashloaders are based on the ARM spec here:
<re_irc> <@t​iwalun:m​> and are implementations of flash loaders, I don't know of anything else except of these and the Pico one.
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<re_irc> <@t​herealprof:m​> jamesmunns: ```
<re_irc> <@t​herealprof:m​> -0.2% 100.0% 824B .text section size, the file size is 323.5KiB
<re_irc> <@t​herealprof:m​> +0.2% 100.0% 748B .text section size, the file size is 319.3KiB
<re_irc> <@t​herealprof:m​> jamesmunns: But if you look at the implementation...
<re_irc> <@t​herealprof:m​> IterMut { inner: Item { opt: self.as_mut() } }
<re_irc> <@t​herealprof:m​> }
<re_irc> <@t​herealprof:m​> pub fn iter_mut(&mut self) -> IterMut<'_, T> {
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<re_irc> <@j​amesmunns:m​> I rescind my "that makes sense"
<re_irc> <@j​amesmunns:m​> I'm now down to wild guesses :D
<re_irc> <@w​illeml:m​> Finally made a pr of my port of samcrow’s fmc lcd driver from stm32f4 to the stm32f7 repo
<re_irc> <@w​illeml:m​> I added them as coauthor to the commit because I wasn’t sure how else to credit them in the commit history…
<re_irc> <@w​illeml:m​> (All I did was some copy pasting and refactoring)
<re_irc> <@t​herealprof:m​> Nice!
<re_irc> <@z​acck:m​> Hi people 👋, I wonder if I can get some help with a driver I am trying to build for the St25ru3993 which is a RFID reader. Communication with the host is done via SPI and I reckon I have all the hardware set up correctly, However whenever I try to read a register from...
<re_irc> ... the device I always receive a static `FF` or 255
<re_irc> <@z​acck:m​> Here is how my code for the driver and the application currenly looks like
<re_irc> <@z​acck:m​> Any sort of help or direction is appreciated.
<re_irc> <@z​acck:m​> Thank you! 📿
<re_irc> <@z​acck:m​> Thank you! 🙏
<re_irc> <@a​damgreig:m​> Zacck Osiemo all FF might indicate a bad connection or the device just not responding or not actually being enabled or selected, so it's hard to know what exactly is going wrong, do you happen to have access to an oscilloscope or logic analyser or anything they would let you see what is happening on the SPI...
<re_irc> ... bus?
<re_irc> <@t​herealprof:m​> Zacck Osiemo: A simple thing to check (and often a culprit) is the state of the ~CS line. If you're using some dev board it's almost certainly exposed and you will need to explicitly pull it low.
<re_irc> <@a​damgreig:m​> They do pull it low between each transaction
<re_irc> <@t​herealprof:m​> Ah, sorry, just noticed the code linked above.
<re_irc> <@t​herealprof:m​> Is it the correct GPIO? 😅
<re_irc> <@a​damgreig:m​> oh, that DSP example I did earlier can actually be done without unsafe at all,
<re_irc> <@a​damgreig:m​> that's nice, good job rust
<re_irc> <@a​damgreig:m​> even spookier ratio of rust to assembler though lol
<re_irc> <@z​acck:m​> adamgreig: None at the moment I can perhaps find ont
<re_irc> <@a​damgreig:m​> that can be helpful just to quickly check the pins into the RFID reader are all being driven like they should, but otherwise I would carefully check all the wiring and the pin assignments in your code
<re_irc> <@z​acck:m​> Let me recheck my wiring
<re_irc> <@t​herealprof:m​> adamgreig: Hm, I'm still seeing `unsafe` in `fn qadd16` or do you mean something else?
<re_irc> <@a​damgreig:m​> oh, yea, forgot that, I mean the packing into u32 which used to be unsafe { *(self as *const _ as *const u32) }
<re_irc> <@a​damgreig:m​> still needs the inline asm and its unsafe
<re_irc> <@a​damgreig:m​> it's a bit more fragile though, you need that &0xFFFF or it fails to fully optimise it
<re_irc> <@t​herealprof:m​> Yeah, I was actually wondering about how to get to the necessary IR to make that magic happen in LLVM.
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<re_irc> <@a​damgreig:m​> that would be nice, I haven't managed to get it to generate any of the _16 or _8 instructions so far, not sure it knows how
<re_irc> <@z​acck:m​> adamgreig: Pin was loose, I get replies now :cele
<re_irc> <@t​herealprof:m​> There're basically two ways to success: Either we recombine 2/4 suitable sadd isns into a single operation in LLVM (which looks gnarly) or we get Rust to do generate IR to use `v2i16` instead of 2 `i16` types.
<re_irc> <@t​herealprof:m​> There're an unstable `#[repr(simd)]` but it actually pessimizes the code since it's not using registers at all.
<re_irc> <@a​damgreig:m​> yea, it has stuff like
<re_irc> <@a​damgreig:m​> but they're all for 64-bit values that only work on "big arm"
<re_irc> <@a​damgreig:m​> maybe core::arch::arm could gain some int16x2 and int8x4 and uint16x2 and uint8x4 types that pack into u32?
<re_irc> <@a​damgreig:m​> basically that's a full set of NEON intrinsics and we'd want the same but for the ARMv7-M/ARMv8-M DSP extension
<re_irc> <@t​herealprof:m​> That certainly makes sense but I'm a bit cautious about `#[repr(simd)]`. I'm not sure why it would behave differently in those intrinsics than in a custom stuct.
<re_irc> <@a​damgreig:m​> there's and so on
<re_irc> <@a​damgreig:m​> I'm not really sure why you can't just use repr(packed) but I guess the point is all the interior elements are still well-aligned
<re_irc> <@t​herealprof:m​> At the moment if you pass a `#[repr(simd)]` type it always seems to go through memory, not via register.
<re_irc> <@a​damgreig:m​> and on armv7-m/v8-m the simd instructions use regular general purpose registers, not special dsp registers
<re_irc> <@t​herealprof:m​> When the LLVM PR is merged (approved already) I can add the lowering of the `v2i16` and `v4i8` types but we'll still need to figure out how to actually provide them to LLVM.
<re_irc> <@t​herealprof:m​> (the absence of all of this is so weird, there's so much low hanging fruit which should provide a noticeable benefit to a lot (dare I say all?) application compiled for ARM)
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<re_irc> <@t​herealprof:m​> Embedded coincidentally profits the last due to being Cortex-M4 and up only. 😅
<re_irc> <@a​damgreig:m​> does normal ARM include the thumb DSP extensions?
<re_irc> <@a​damgreig:m​> plenty of applications using cm4 and cm7!
<re_irc> <@a​damgreig:m​> therealprof: nice!! don't forget v2u16 and v4u8 too
<re_irc> <@a​damgreig:m​> like, ARMv7-A doesn't have SSUB16 or QADD16 or anything like that, as far as I can tell?
<re_irc> <@l​ulf_:m​> cr1901: cr1901: MathiasKoch FYI I've added blocking support to drogue-tls and it should also compile with rust stable (async requires nightly still). Going to publish a 0.2.0 version of the crate later today.
<cr1901> Good stuff (I'm stuck on nightly anyway, don't worry). Thanks for your effort
<re_irc> <@t​herealprof:m​> adamgreig: They don't exist in LLVM IR, they only have "integer".
<re_irc> <@a​damgreig:m​> I see
<re_irc> <@t​herealprof:m​> adamgreig: Not sure about ARMv7-A but I'm assuming I do as well since they's no gate in LLVM code as far as I can see. I checked ARMv8-A as I pointed out the other day and they are mandatory instructions (although I haven't checked whether they have all of them).
<re_irc> <@a​damgreig:m​> So no uadd8?
<re_irc> <@t​herealprof:m​> adamgreig: That's done via the IR mnemonics. The parameters are all 🤷‍♂️.
<re_irc> <@t​herealprof:m​> It's `@llvm.usub.sat.i8` vs `@llvm.ssub.sat.i8`
<re_irc> <@a​damgreig:m​> aah, I still had case sensitive search turned on 😐️ v7-A does have all the v7E-M DSP instructions
<re_irc> <@a​damgreig:m​> so yea, that makes it even weirder that LLVM doesn't...
<re_irc> <@m​athias_koch:m​> Ulf Lilleengen: Awesome! Thanks for the update! Now i just need AWS to actually support TLS1.3.. ☹️ Don't suppose you can help with that? :p
<re_irc> <@a​damgreig:m​> they were added in ARMv5TE so I think ARMv6-A and ARMv7-A both have them
<re_irc> <@t​herealprof:m​> adamgreig: I concur.
<re_irc> <@a​damgreig:m​> so, wow, yea, anyone on ARM should expect to benefit, which is also a good reason to get them into core::arch::arm I guess
<re_irc> <@a​damgreig:m​> so long as it doesn't try to emit them for thumbv6m-none-eabi, heh
<re_irc> <@t​herealprof:m​> That works just fine.
<re_irc> <@t​herealprof:m​> For single values the IR is produced correctly which is the reason why were seeing 2 of those instructions in my 2D Coordinate example code.
<re_irc> <@t​herealprof:m​> Only for unsigned addition the lowering doesn't exist so it's emulated with regular instructions.
<re_irc> <@t​herealprof:m​> But now the question is, how can get Rust to pack the coordinates into a one register of type v2i16 instead of 2 registers of type i16 (and whithout going over memory like `#[repr(simd)]` does).
<re_irc> <@t​herealprof:m​> Unfortunately godbolt IR generation is super flaky, sometimes it works, sometimes it doesn't...
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<re_irc> <@f​irefrommoonlight:m​> FYI Digikey just stocked some Stm32s
<re_irc> <@f​irefrommoonlight:m​> I just scored some L4s that have been out of stock for months
<re_irc> <@r​yan-summers:m​> You should be charging people for that intel ;)
<re_irc> <@a​damgreig:m​> I can just imagine the armed guards with a briefcase full of waffle trays
<re_irc> <@f​irefrommoonlight:m​> I bought first and am now looking more broadly: it may have just been for the specific model, or a small handful. Most are still 0 stock. L443CCT (L4 with 256k flash in qfp48) has about 1700 left
<re_irc> <@f​irefrommoonlight:m​> That happens to be the one I designed for. Not total coincidence since that's the page I've been F5ing most
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<re_irc> <@a​nahata:m​> I didn't realize STM32s are in such demand. I have one I'm not using, an STM32F3Discovery, and I'd be happy to send it to someone who's going to make use of it. It's lightly used, mostly I got it to go through the discovery book, but got a bit lost around chapters 6/7 and went off and did my own things
<re_irc> <@t​herealprof:m​> adamgreig: Hm....
<re_irc> <@t​herealprof:m​> Not quite sure how that is supposed to work.
<re_irc> <@a​damgreig:m​> hmmm
<re_irc> <@a​damgreig:m​> dunno, they don't show up on
<re_irc> <@a​damgreig:m​> maybe due to
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<re_irc> <@t​herealprof:m​> Maybe too new?
<re_irc> <@f​irefrommoonlight:m​> anahata: Dev boards are still easy to get. It's bare chips that aren't
<re_irc> <@a​nahata:m​> ah, okay, thank you for clarifying
<re_irc> <@f​irefrommoonlight:m​> But that's nice of you to offer that!
<re_irc> <@f​irefrommoonlight:m​> For some context, [here is the Digikey search page for STM32]( The ones available at quantities >100 fill up about 1.5 pages, and there's 0...
<re_irc> ... stock page page 3. This is for a large and diverse product lineup, from the biggest distributor for people who can't buy direct from manufacturer. And most of the available ones are in BGA packages, which are tough to inspect without an X-ray machine
<re_irc> <@t​hejpster:m​> Damn. I put in an order on Monday.
<re_irc> <@t​hejpster:m​> In the UK you need to get it up to £33 to get free postage
<re_irc> <@t​hejpster:m​> I need F031s in a QFP32, which is normally about £1. They only have one QFP32 in stock which is an L071, and they're £4.
<re_irc> <@t​hejpster:m​> RS in the UK seem to have some stock
<re_irc> <@a​nahata:m​> Still expensive, though, ouch
<re_irc> <@t​hejpster:m​> Not as bad as LCSC. They want $7 a piece!
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<re_irc> <@y​atekii:m​> lol
<re_irc> <@y​atekii:m​> we have a component in our product that is 10$ instead of 20Cts :D
<re_irc> <@y​atekii:m​> fun times
<re_irc> <@y​atekii:m​> should have invested in the MCU trade
<re_irc> <@d​irbaio:m​> oof 50x? We have one that did a 20x 🤣
<re_irc> <@d​irbaio:m​> it's getting the axe in the next revision ☠️
<re_irc> <@f​irefrommoonlight:m​> That sucks!
<re_irc> <@f​irefrommoonlight:m​> In surprised about LCSC being more expensive. They're generality cheaper for me compared to Digikey, but spottier stock
<re_irc> <@y​atekii:m​> dirbaio: yeah x50 was a new record ... I think our record before that was was x18 before that
<re_irc> <@a​damgreig:m​> LCSC are _usually_ cheaper but they haven't been afraid to bump prices on the stuff that's out of stock everywhere else
<re_irc> <@n​fd:c​> it's so weird to me that no manufacturer seems to want to make those despite the big hobbyist demand
<re_irc> <@t​herealprof:m​> nfd: OTOH designing PCBs has become so easy and cheap, that many hobbyists simply have moved over to doing that. Plus the "big" hobbyist market is still a tiny piecemeal business compared to the huge industry business buying magnitudes more units.
<re_irc> <@n​fd:c​> yeah, like, tons of hobbyists seem completely happy with Arduino-compatible/RasPi-esque boards because you can go from 0 to blinking an LED in approximately 0.5 A presses. and that's cool and i'm happy to support them in that/those hobbyists in that hobbyisting
<re_irc> <@n​fd:c​> it just feels weird to me that there was like *one* nicely breadboardable M0 package and they're just done with it, whether it's huge business or no
<re_irc> <@a​damgreig:m​> but also loads of hobbyists these days are designing their own PCBs using the same BGA parts going into phones, how many hobbyists are left needing DIP chips?
<cr1901> Me
<re_irc> <@a​damgreig:m​> might be a chicken and egg thing where no one makes DIP-packaged cortex MCUs though....
<cr1901> Because fuck BGA
<re_irc> <@a​damgreig:m​> hah, I mean, fair
<re_irc> <@a​damgreig:m​> 0.8mm tqfp isn't so bad though
<re_irc> <@a​damgreig:m​> do msp430 come in DIP?
<cr1901> yes, the G-series does at least
<re_irc> <@n​fd:c​> like, my intro to embedded dev was taking an lpc1114 from cross-compiler/manual to multitasking
<re_irc> <@a​damgreig:m​> wow, cool
<re_irc> <@n​fd:c​> i don't feel like that's an experience you're likely to *get* when you're baking stuff into chips
<re_irc> <@a​damgreig:m​> how do you mean?
<cr1901> Anyways surface mount I can do w/ a toaster oven set to 450F. But BGA is awful for hobbyists
<re_irc> <@a​damgreig:m​> you could take an stm32f0 from cross-compiler to multitasking just the same
<re_irc> <@n​fd:c​> sure thing
<re_irc> <@a​damgreig:m​> cr1901: I bet if you just put a bga on your pcb with some flux and in your toaster oven it would probably be ok
<re_irc> <@t​herealprof:m​> Yeah, maybe, but BGA is really extreme.
<re_irc> <@a​damgreig:m​> but definitely a lot more work than hand soldering a larger package with exposed leads for sure
<re_irc> <@a​damgreig:m​> they do SOIC-8 stm32g0, that's pretty close to a dip!
<re_irc> <@t​herealprof:m​> nfd: There're some chips in quite hand solderable packages like a STM32F042F6.
<cr1901> The amount of flux you need to put under the BGA pads needs to be carefully controlled. Certainly within the realm of human precision, but I manage to screw it up anyway
<re_irc> <@t​herealprof:m​> But even soldering a QFP32 package to an DIP adapter board is easily doable for anyone with a simple solder iron.
<re_irc> <@a​damgreig:m​> maybe they should do a DIP stm32g0 anyway :P
<re_irc> <@a​damgreig:m​> once you have it ready for a soic-8 leadframe surely it's easy to DIP-8 package it
<cr1901> LPC810 was the last DIP ARM I'm aware of
<cr1901> discontinued in 2017 I think :/
<cr1901> Also, the SVDs NXP provided were shit
<re_irc> <@n​fd:c​> therealprof: looks pretty nice...
<re_irc> <@t​herealprof:m​> adamgreig: It's still a lot of extra work for something which will not sell in millions.
<re_irc> <@t​herealprof:m​> nfd: That was my goto chip for a long time, it's very feature packed and can even do USB without external crystal.
<re_irc> <@n​fd:c​> doesn't look *super* available atm but
<re_irc> <@a​damgreig:m​> +1, love the f042, at least when you can get it
<re_irc> <@t​herealprof:m​> nfd: Yeah, that's a very real general problem at the moment.
<re_irc> <@a​damgreig:m​> I think the new g0 chips are probably an exciting more modern option with generally the same or better features
<re_irc> <@n​fd:c​> lol yup
<re_irc> <@n​fd:c​> you'd think semiconductors were as valuable as toilet paper
<re_irc> <@n​fd:c​> hmm
<re_irc> <@n​fd:c​> dip-8 or no, are any of y'all aware of any chips nicely broken out to be solderless breadboard-friendly without extra miscellany?
<re_irc> <@n​fd:c​> ideally pushing the unit price under around $2
<re_irc> <@n​fd:c​> think classroom settings
<re_irc> <@t​herealprof:m​> At the moment? No. 2 years ago I'd say it would have been possible to prepare something roughly at that pricepoint.
<re_irc> <@t​herealprof:m​> At the moment your best shot in the <<$10 range would be a presoldered kit, like Rapberry Pi Pico, USB-C Pill, or a LPC845BRK.
<re_irc> <@n​fd:c​> heh. even the 845 isn't in BYOMOSFET territory 😛
<re_irc> <@t​herealprof:m​> Hm, I've misplaced 20 or so STM32F072... I need to better watch out for that silicon gold... 😅
<re_irc> <@n​fd:c​> tru
<re_irc> <@n​fd:c​> halfway tempted to grab some of those for funsies
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<re_irc> <@t​halesfragoso:m​> adamgreig: Their 255 bytes i2c is weird, can just fire the DMA and forget
<re_irc> <@t​halesfragoso:m​> Although is the same in several other families :/
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<re_irc> <@l​achlansneff:m​> dirbaio: Should there be a trait for reading n bytes from SPI, but not writing it to a slice?
<re_irc> <@t​halesfragoso:m​> Btw, I wanted to test my driver for using more than 255 bytes transfer, but I ssd1306 only does several 17 bytes transfers instead of everything at once
<re_irc> <@t​halesfragoso:m​> Probably because of the lack of write_vectored or something
<re_irc> <@t​halesfragoso:m​> Probably could do with WriteIter though, but not with DMA
<re_irc> <@t​herealprof:m​> thalesfragoso: Yeah, legacy.
<re_irc> <@t​halesfragoso:m​> Is it some hardware limitation of just because it needs the pre-pend the data byte ?
<re_irc> <@t​herealprof:m​> It's just because of the extra buffering required for the prepended byte, yes.
<re_irc> <@t​herealprof:m​> It's a compromise between overhead and efficiency.
<re_irc> <@t​halesfragoso:m​> Maybe WriteIter would work ?
<re_irc> <@t​herealprof:m​> Yes, but with DMA? 😉
<re_irc> <@t​halesfragoso:m​> Yeah, no DMA, but most traits aren't implemented with DMA though
<re_irc> <@t​halesfragoso:m​> But we might want a write_vectored in e-h
<re_irc> <@t​herealprof:m​> I used the driver as a playground for `display-interface` so we could get rid of the built-in I2C/SPI abstractions but we never changed the way of operation.
<re_irc> <@l​achlansneff:m​> Err, should most of these Read and Write traits be replaced with the canonical `Read`, `Write`, `AsyncRead`, and `AsyncWrite` traits?
<re_irc> <@l​achlansneff:m​> Ignoring for the fact that those aren't available at the moment on no_std
<re_irc> <@t​herealprof:m​> Lachlan Sneff: ?
<re_irc> <@l​achlansneff:m​> I just thought of that. Most of the Read and Write traits in embedded-hal are almost, but not quite the same as Read and Write if the error were an associated type
<re_irc> <@t​herealprof:m​> thalesfragoso: You can write your own `d-i` driver though which DMAs the data out.
<re_irc> <@l​achlansneff:m​> Lachlan Sneff: Actually this is dumb, nvm
<re_irc> <@l​achlansneff:m​> Ignore me
<re_irc> <@t​herealprof:m​> Lachlan Sneff: It might be possible for some (and there's e.g. Write adapters for serial) but for others you need a different interface or a special adapter in order to do that. E.g. I2C requires an address to be supplied.
<re_irc> <@d​irbaio:m​> Lachlan Sneff: what do you mean?
<re_irc> <@d​irbaio:m​> Lachlan Sneff: I don't think this would really work, the protocols have quirks
<re_irc> <@d​irbaio:m​> - as already stated, i2c requires an address
<re_irc> <@d​irbaio:m​> - spi transfer is not the same as spi write, spi read (or any combination thereof)
<re_irc> <@d​irbaio:m​> - i2c write_read is not the same as i2c write, then i2c read
<re_irc> <@d​irbaio:m​> plus they can do short reads/writes which is annoying and doesn't make sense when taking directly to the hardware
<re_irc> <@l​achlansneff:m​> dirbaio: For example, I know how many bytes are on the wire, but I want to ignore them because I only have so much space to store them.
<re_irc> <@l​achlansneff:m​> But I still need some data at the end of the packet.
<re_irc> <@d​irbaio:m​> oh.. dunno, seems very niche
<re_irc> <@l​achlansneff:m​> Yeah, not very common probably
<re_irc> <@l​achlansneff:m​> Implementation would just be a DMA transfer with both pointers set to null though
<re_irc> <@f​irefrommoonlight:m​> cr1901: try QFN
<re_irc> <@f​irefrommoonlight:m​> Its auto-centering is magic. If it doesn't work, apply flux to edges, and tap with iron
<re_irc> <@t​halesfragoso:m​> Lachlan Sneff: That would cause an error, no ?
<re_irc> <@t​halesfragoso:m​> Usually bus error on the DMA
<re_irc> <@f​irefrommoonlight:m​> adamgreig: I'm probably going to use a G0 next time I need a super-cheap MCU
<re_irc> <@l​achlansneff:m​> thalesfragoso: Certainly might, not sure
<re_irc> <@f​irefrommoonlight:m​> dirbaio: What's the difference between SPI transfer, and write followed by read? (Assuming the write is a single word)
<re_irc> <@d​irbaio:m​> transfer writes and reads at the same time
<re_irc> <@f​irefrommoonlight:m​> Ah gotcha! I've been doing mostly blocking
<re_irc> <@d​irbaio:m​> yeah even blocking transfer reads and writes at the same time
<re_irc> <@f​irefrommoonlight:m​> Now that you mention it, the DMA recipe is to kick off in a way where they run concurrently
<re_irc> <@f​irefrommoonlight:m​> I2C has further subtleties
<re_irc> <@f​irefrommoonlight:m​> I think re autoending
<re_irc> <@d​irbaio:m​> transfer of 1 byte does 8 clocks on the bus, shifting out a bit AND shifting in a bit at every clock cycle
<re_irc> <@f​irefrommoonlight:m​> Sweet
<re_irc> <@d​irbaio:m​> write 1 byte + read 1 byte will do 16 clocks, first shifting out the write, then shifting in the read
<re_irc> <@f​irefrommoonlight:m​> Thank you for the expalanation!
<re_irc> <@f​irefrommoonlight:m​> I may need to adjust some code...
<re_irc> <@d​irbaio:m​> hahaha :)
<re_irc> <@f​irefrommoonlight:m​> (FYI, doing the read after teh write works for SPI blocking, but it sounds like it's inefficient)
<re_irc> <@f​irefrommoonlight:m​> And I2C will flat out not work if you try it that way
<re_irc> <@f​irefrommoonlight:m​> due to the termination
<re_irc> <@d​irbaio:m​> firefrommoonlight: implementing Transfer with Write and Read?
<re_irc> <@f​irefrommoonlight:m​> Yea
<re_irc> <@d​irbaio:m​> it's not just slow, it won't work
<re_irc> <@d​irbaio:m​> it does a different thing
<re_irc> <@f​irefrommoonlight:m​> Hmm....
<re_irc> <@f​irefrommoonlight:m​> Seems to work for me, unless I'm missing something
<re_irc> <@f​irefrommoonlight:m​> On several devices
<re_irc> <@d​irbaio:m​> you don't choose when your slave chip sends you the data
<re_irc> <@f​irefrommoonlight:m​> Might be working by coincidence.
<re_irc> <@f​irefrommoonlight:m​> Is this approach from `embedded-hal`'s default transfer impl wrong?
<re_irc> <@d​irbaio:m​> nb::spi::FullDuplex is specified to write+read at the same time
<re_irc> <@d​irbaio:m​> when you do `write`, it'll do 8 cycles writing the value, AND reading a value back
<re_irc> <@d​irbaio:m​> it stores that value somewhere
<re_irc> <@d​irbaio:m​> and with `read` you just get that value out, it doesn't do another 8 clock cycles
<re_irc> <@d​irbaio:m​> so nb `write` then `read` really is writing+reading at the same time
<re_irc> <@f​irefrommoonlight:m​> Doesn't this `nb::block!(self.write(word.clone()))?;` block during the write, and the read can't start until the write is complete?
<re_irc> <@d​irbaio:m​> but blocking `write` then `read` is not
<re_irc> <@d​irbaio:m​> nb::block!(self.write(word.clone()))?; blocks during the write AND does a read at the same time without you asking for it
<re_irc> <@f​irefrommoonlight:m​> so it assumes `write` does a read too?
<re_irc> <@d​irbaio:m​> `` pops that byte out
<re_irc> <@f​irefrommoonlight:m​> Actually, now that I look at the code I'm using on stm32, the first step in the write is to read from SR register
<re_irc> <@f​irefrommoonlight:m​> Thank you. I'm going to do some digging and try to learn more about this. I evidently have some gaps
<re_irc> <@d​irbaio:m​> not your fault... I find that nb spi trait to be ultra confusing too
<re_irc> <@f​irefrommoonlight:m​> I think what happened is I blindly aped it without understanding, with the actual write and read code coming from a STM32 RM
<re_irc> <@d​irbaio:m​> and it's very underspecified
<re_irc> <@d​irbaio:m​> can you call write n a loop without ever reading? docs suggest you can, but impls explode if you try that
<re_irc> <@f​irefrommoonlight:m​> This could be related to why I'm struggling wtih SPI DMA
<re_irc> <@f​irefrommoonlight:m​> Haven't tried - the `write_one` method I've been using starts with a read
<re_irc> <@f​irefrommoonlight:m​> Might give it a shot just to prove it to myself, but I'm confident you're right
<re_irc> <@d​irbaio:m​> dma, fun
<re_irc> <@d​irbaio:m​> what chips are you targeting for dma?
<re_irc> <@f​irefrommoonlight:m​> I'm trying to get it to work with an SPI display
<re_irc> <@d​irbaio:m​> what stm32 families I mean
<re_irc> <@f​irefrommoonlight:m​> Any/all
<re_irc> <@f​irefrommoonlight:m​> At least ones F3 and newer
<re_irc> <@f​irefrommoonlight:m​> Testing on L4. (I say any/all since the SPI and DMA periphs are very similar across)
<re_irc> <@f​irefrommoonlight:m​> With some quirks like L4 needing a special channel select that none of the others have, and the newer ones using DMAMUX
<re_irc> <@d​irbaio:m​> lol, no they aren't :o
<re_irc> <@f​irefrommoonlight:m​> H7 has some diff status codes. What significant differences have you found?
<re_irc> <@f​irefrommoonlight:m​> (Obviously this could be related to why I can't get it working...)
<re_irc> <@f​irefrommoonlight:m​> And G0's missing some DMA channels
<re_irc> <@d​irbaio:m​> there's at least 5 variants 🤣
<re_irc> <@f​irefrommoonlight:m​> Ok, but what are the differences, and are you referring to SPI or DMa?
<re_irc> <@d​irbaio:m​> thalesfragoso and Bob McWhirter are having lots of fun with it in embassy
<re_irc> <@d​irbaio:m​> DMA
<re_irc> <@d​irbaio:m​> BDMAv1: F0, F1, F3, L1
<re_irc> <@d​irbaio:m​> hardcoded set of peripherals. Two peripherals that are associated
<re_irc> <@d​irbaio:m​> to the same DMA channel can't be used with DMA at the same time, AT ALL.
<re_irc> <@d​irbaio:m​> no request selection capabilities. Each DMA channel is the OR of a
<re_irc> <@f​irefrommoonlight:m​> The L0, L4 caveat is the one I mentioned. I haven't implemented for F4, F7, F2
<re_irc> <@f​irefrommoonlight:m​> So that's probably consistent with what I'm doing
<re_irc> <@d​irbaio:m​> note that "BDMA" is called "DMA" by ST unless in the H7
<re_irc> <@d​irbaio:m​> in embassy we decided to call it "BDMA" in all to prevent going crazy
<re_irc> <@f​irefrommoonlight:m​> I just looked at my notes: I skipped H7 because I couldn't figure it out!
<re_irc> <@f​irefrommoonlight:m​> The L4 thing is weird - why do you need to specify the channel when you have no choice?!?!
<re_irc> <@d​irbaio:m​> you do have a choice, that's the point
<re_irc> <@f​irefrommoonlight:m​> I have 2 broad categories: DMAMUX and non-DMAMUX, with L4 being an exception to the latter with an additional step
<re_irc> <@d​irbaio:m​> there's these 5 categories :P
<re_irc> <@f​irefrommoonlight:m​> What I'm tracking: There's a CxS field you set to pair a channnel to which peripheral is on it
<re_irc> <@f​irefrommoonlight:m​> But each periph only has 1 option for channel
<re_irc> <@f​irefrommoonlight:m​> RM0394, Table 41
<re_irc> <@f​irefrommoonlight:m​> If I'm missing something, this could absolutely explain why my DMA isn't going well
<re_irc> <@f​irefrommoonlight:m​> Other than the CxS (x being channel num), what other L4 steps are there?
<re_irc> <@d​irbaio:m​> nope, there are some exceptions :D
<re_irc> <@d​irbaio:m​> for example: i2c1_tx can go in DMA1_CH6 or DMA2_CH7
<re_irc> <@f​irefrommoonlight:m​> Gotta run for 30 mins I'll take a look!
<re_irc> <@d​irbaio:m​> if peripheral requests were ORed together like in BDMAv1 (f0, f1, f3, l1), if you're using I2C1_TX for DMA1_CH6, it would also spam DMA2_CH7 with requests so you wouldn't be able to use it for something else
<re_irc> <@d​irbaio:m​> in BDMAv2 you can set DMA2_CH7's CSELR to something else so you can still use it
<re_irc> <@d​irbaio:m​> and there's quite a few more of these
<re_irc> <@d​irbaio:m​> for example
<re_irc> <@d​irbaio:m​> (search for `dma_channels`)
<re_irc> <@b​obmcwhirter:m​> At least flavors of bdma are 3 of the 5
<re_irc> <@d​irbaio:m​> and of dma too 🤣
<re_irc> <@d​irbaio:m​> intersecting in the H7 which has both
<re_irc> <@t​halesfragoso:m​> And you still have chips in the same family that have chsl while others don't
<re_irc> <@f​irefrommoonlight:m​> dirbaio: I'm only tracking CH6
<re_irc> <@f​irefrommoonlight:m​> CH7 is for the Dma2 periph
<re_irc> <@f​irefrommoonlight:m​> So there are still 0 degrees of freedome
<re_irc> <@f​irefrommoonlight:m​> Ah I see your explanation now. Makes sense. awkward. I think my code there is right though
<re_irc> <@f​irefrommoonlight:m​> Mainly because I cheated and didnt' implement DMA2 for any MCU...
<re_irc> <@f​irefrommoonlight:m​> Broken down, I've implemented on G0, G4, L4, L5, WB, WL, and F3. F3 doesn't use DMAMUX. L4 is like F3, but also has that CxS thing we just talked about. The rest use DMAMUX
<re_irc> <@d​irbaio:m​> :)
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<cr1901> f​irefrommoonlight: QFN is fine, I have an okay success rate w/ that
<re_irc> <@b​obmcwhirter:m​> So much DMA
<re_irc> <@b​obmcwhirter:m​> I think of DMAMUX as a bolt on to BDMA this evening.
<re_irc> <@b​obmcwhirter:m​> Fancy chsel