sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<sorear> zicfilp requires a different definition of tail. fortunately, it's a psuedoinstruction, so there's no hardware contradiction
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<courmisch> sorear: assembler can't just start clobbering different registers
<sorear> ok. what does the assembler do?
<courmisch> if somebody uses tail for non-ABI calls, that could break
<courmisch> at least gas seems to use x6 as RVI states it should
<sorear> regardless of -march?
<courmisch> I don't have a version recent enough to try with zicfil, if it even exists
<sorear> the ISA extension specs don't actually have the authority to dictate assembler behavior so what matters is what's implemented
<sorear> there's an assembler manual spec which should have authority but it hasn't been updated in years
<courmisch> sorear: the asm manual also dictates x6/t1
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<Tenkawa> Esmil: strange happening with your git source fior 6.10 and I wanted to see if its just me.
<Tenkawa> the 6.10.0-rc7 one boots/runs fine... but soon as I updated it.... it fails
<Tenkawa> boot appears to see no pci bus...
<Tenkawa> I used your 6.10.0-rc1 version of the jh7110 branch oand had it up to rc7 with no problem... I think I might see whats wrong. I think I picked up the visionfive branchinstead of jh7110 for this test
<Tenkawa> trying another buildd
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<drewfustini> interesting to see the SiFive P550 core board is available on Arrow https://www.arrow.com/en/products/hf106-000/sifive-inc
<drewfustini> the product page is a bit bar but this related page has the info
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