sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<courmisch> just when I was thinking to drop V subsets from FFmpeg, Linux kernel adds them
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<palmer> courmisch: ya, just trying to make life complicated ;)
<courmisch> we have only 31 bits for CPU caps here because of some disagreeable hysterical raisins :(
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<conchuod> palmer: was that starfive cache thing cos builds were breaking?
<palmer> conchuod: ya, it uses some 64-bit IO stuff that just fails on 32
<conchuod> I don't really want to send another PR this week with just that, maybe I can bounce it on to Arnd.
<palmer> Not sure if it's supposed to have 32-bit control registers on 32-bit systems? Or maybe or just oeabt exist on those
<palmer> I can send it if you want?
<conchuod> I think it doesn't even exist!
<palmer> I'm sending another one anyway...
<conchuod> Exist on 32-bit systems*
<conchuod> Uh, ye. I'll ack it.
<conchuod> Done
<Esmil> palmer: is the 39 -> 39ULL really needed? I'd think the GENMASK macro would take care of that
<conchuod> I think you need to use GENMASK_ULL actually, no?
<Esmil> yeah, that would make sense
<palmer> actually I thought I'd dropped it from the patch, with no 64-bit stuff it doesn't matter (it fixed the first error, but then the readq/writeq makes it useless)
<palmer> so I can send a v2 with that dropped?
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<conchuod> Sure
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<palmer> OK
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<courmisch> I don't really get the point of Zve64d. If you're going to support 64-bit elements, what's the point of 64-bit "vectors"
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<conchuod> I figure most of those subsets are gonna be deadge
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<courmisch> yeah but when I see a professional adding them to the kernel, I wonder if they know something that I don't
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<palmer> there's some DSP-type stuff in the V extension -- stuff like saturating ops
<conchuod> courmisch: I figure that having them in their product line is not much work for sifive, so they might as well. If we support one subset, we might as well support em all.
<conchuod> If you're doing zve32d, then f aint that bad etc.
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<courmisch> palmer: don't get me started on the lack on signed-to-unsigned narrowing clip
<courmisch> palmer: also, hmm, do you really want to double, triple or quadruple the register bank on embedded just to get a few extra arithmetic functions? I figure hypothetical P or Zvinx would be more sensible
<palmer> Ya, it really sucks that P got so handicapped in favor of V
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<JohnHenry> every chip should be a Cray supercomputer, right?
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<courmisch> If every computer were the same, most of us would lose their jobs.
<courmisch> So, meh
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<courmisch> isn't there a contradiction between zicfilp and the base spec?
<courmisch> the old says that `tail` clobbers x6 and the new one says x7
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