sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<conchuod> palmer: could you clarify if this applies to ISA extensions or to SBI extensions too: https://docs.kernel.org/riscv/patch-acceptance.html
<palmer> SBI too
<palmer> there's been some posts
<conchuod> :+1:
<conchuod> Well that's good to know at least
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<conchuod> Bit restrictive maybe on the SBI front since an extension may not go remotely near arch code at all (and maybe hard to police since there's no maintainers regex or w/e to ensure someone sees those patches)
<conchuod> palmer: in other news, if you're doing your rc5 fixes today, could you pick up Drew's version of your zicbom fixes?
<palmer> the SBI stuff used to not be so restrictive, bet there's been way too many breaking changes to the SW-style specs
<palmer> it's kind of a bummer, but I'm not sure how else to go about it
<conchuod> Better to have a clear policy of no, rather than fight it every time
<palmer> ya, that's sort of where we ended up -- it's all the same this way, so it's easier
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<palmer> there's still kind of a grey area, as "freeze" is a lot weaker of a term for the SW specs, but I'm not sure what to do about that
<conchuod> I am not going to do this obviously, but we could "sneak" around since we are entirely inside a mbox driver
<conchuod> But the Andes thing from today is doing non-zicbom, non-coherent dma in arc/riscv & something something goose, gander
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