sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Backup if libera.chat and freenode fall over: irc.oftc.net
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<enthusi> I wrote a little bare metal lz4 decoder for RV32I(C) with simple example case
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<carado> anyone know if there's a way to restrict llvm, or rustc, or gcc, to only use some of the registers ? such as only x0 to x8, and not the rest
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<jrtc27> this sounds like an A/B problem
<jrtc27> what are you trying to achieve by doing this?
<jrtc27> are you aware of how ABIs work and that what you're asking for can be impossible depending on what set of registers you choose?
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<carado> what i'm trying to achieve is use risc-v as an intermediary representation for a custom instruction set for a vm i'm making, rather than having to implement a whole new llvm target
<carado> i'm aware of ABIs yeah
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<jrtc27> depending on which registers you want to exclude, you may be able to get away with -ffixed-xN for each xN you want to not use
<jrtc27> but you are not going to have a good time if you exclude any of the argument registers
<jrtc27> which are x10-x17
<carado> well that's fine then, i can just make sure to include those
<carado> thanks
<enthusi> and the C extension also works on a specific subset
<enthusi> s0/1 and a0-a5 iirc
<jrtc27> that's not relevant her
<jrtc27> *e
<dh`> having done somethnig like that long ago, quick recommendation: pick the intermediate target based on how many registers it has
<dh`> it's easy to translate instructions, not so easy to rearrange register usage
<carado> well, if i can reserve registers i'd think that can accomplish the same result
<carado> but yeah otherwise i'll keep that in mind
<dh`> turning off 16 registers you can probably do, but you might find x86_64 or armv7 a better intermediate target (though there are reasons to avoid both)
<dh`> turning off 24 is likely to blow the compiler's mind I suspect
<geist> if it'll even handle it. on other arches (arm64, etc) i've found that gcc and llvm have differing levels of suppot for -ffixed-xN
<geist> clang in particular (and possibly llvm) only lets you set fixed fo some cherry picked ranges
<geist> on arm64 at least. possible it's more generic on riscv implementation (or worse)
<geist> gcc is a bit more flexible there
<carado> llvm does seem to be ignoring some of my overrides
<jrtc27> I think LLVM will just ignore you if you try and reserve a register it's forced to use for ABI reasons
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<carado> i get friendly error messages warning me if i reserve too many argument registers, or x1/x2
<carado> but it's using x18/x19 even if i reserve those, without any message
<jrtc27> ah good
<jrtc27> looks like x1, x2 and x8, plus any argument registers your code ends up needing, give errors
<jrtc27> um, are you sure about that?
<jrtc27> x18 especially is the one that this was added for in the first place
<jrtc27> as using the shadow call stack requires -ffixed-x18
<carado> yeah, hold on
<jrtc27> (don't ask why x18...)
<carado> well that's strange, it seems to work when i compile my rust to llvm ir, and then use llc; but not when i pass the arguments directly through RUSTFLAGS='-C target-feature=+reserve-…'
<carado> oh yeah, nevermind, it does work
<carado> i was checking the wrong elf
<carado> funnily enough i can reserve as much as everything except x1,x2,x8,x9,x10,x11
<dh`> curious about x8/9
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<carado> oh yeah i can disable those too actually
<carado> my bad
<dh`> also I'd be surprised if you don't actually have to keep all of a0-a7; did you test a function with 8 args?
<carado> oh, it does require them when i use more arguments
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<carado> well thanks for the help!
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<dh`> remember it was jrtc27 who pointed out the argument registers, not me :-)
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