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<clever>
anybody here familiar with how irq's work on rv32? linux is throwing an odd error that is getting in my way: [ 0.276729] WARNING: CPU: 0 PID: 1 at kernel/irq/manage.c:2183 request_threaded_irq+0x114/0x204
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<clever>
i think its due to IRQ_PER_CPU_DEVID being set on the irq, but i'm not sure why its fine with the other irq's
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<sorear>
nothing interrupt related is different beyond surface details between rv32 and rv64, at least architecturally
<sorear>
I'm not sure offhand what could be causing linux to behave differently
<clever>
sorear: so far, the only big difference ive discovered, is that the hw timer never calls request_threaded_irq
<clever>
so its avoiding the error, by just not calling the function that throws errors
<clever>
for context, the riscv,clint0 irq's work fine, but a virtio,mmio irq instantly fails upon request
<clever>
ah, because the timer is using request_percpu_irq
<clever>
which makes sense, you want timers to be core-local
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<clever>
sorear: do you have any examples of a non core-local irq that works?
<sorear>
I've never touched the linux core irq code, but I don't remember having difficulty with irqs on rv32 in 2020
<sorear>
when I did fairly extensive testing of the recently merged musl port in qemu
<clever>
has anybody ever gotten virtio-mmio to work in risc-v?
<sorear>
yes
<clever>
sorear: its ugly, but i "fixed" it by just editing virtio-mmio, to use per-cpu irqs!, do you have an example dts of where it works normally? qemu i'm guessing?
<sorear>
yes, qemu. I presume you only have one cpu if there's no functional difference?
<clever>
yeah, i would assume the same
<sorear>
wait, you were working on a custom simulator for some reason - do you have anything to actually deliver global interrupts?
<clever>
but its weird that the driver is "broken" like this
<clever>
sorear: the only irq controller i have, is a child of the cpu 0 node!
<clever>
that smells like a per-cpu irq controller
<sorear>
Core Local INTerrruptor
<clever>
ah, thats what happens when i charge in blindly, and write code without knowing the shorthand!
<clever>
from what i can see, clint is a timer, that generates core-local ints at a defined time, and riscv,cpu-intc is a core-local interrupt controller?
<clever>
and the dts just lacks a global interrupt controller?
<sorear>
you need a PLIC, APLIC, or MSIs to support routing global interrupts to specific cores. I'm not sure if linux supports hooking up general hardware to core-local interrupts (it seems like it should be possible, but the hardware on which it makes sense tends to be too low-spec for linux so I wouldn't personally have prioritized making it work)
<sorear>
virtio-mmio doesn't support MSI but virtio-pci does
<clever>
i guess i can temporarily charge on with it configured as a core-local irq, and when the main dev wakes up, can then look into getting global irq's
<clever>
i dont have a pci bus either, so virtio-pci would be even more work
<sorear>
is there a version of the dts with the virtio-mmio or other device you were trying to use?
<sorear>
virtio-mmio is a "slot" which can be empty, qemu does or did just create 8 of them at fixed addresses regardless of the command line
<clever>
let me pastebin the new dts
<sorear>
I'm wondering how you tried to specify the cpu-intc as an interrupt target
<clever>
i basically just copied what the clint was doing, but youll also see i cleaned up how interrupts are handled, vs what was in github
<sorear>
I'm looking up what <8> means right now but custom core-local interrupts start at a minimum of 16
<clever>
ah
<clever>
i initially tried 42, then noticed that linux seemed to only allocate 32 irq's
<clever>
so i tried 30, and then 8
<clever>
and all of them failed equally
<sorear>
Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt says that custom core-local interrupts (those other than the standard timer, standard IPI, and standard chaining point for a PLIC or APLIC) are not supported at all, but this is incompatible with the functionality of CONFIG_RISCV_M_MODE and also doesn't seem to be checked anywhere
<sorear>
I take it you're not actually delivering interupts in rv32ima yet
<clever>
no new interrupts, just the existing clint ones
<clever>
`sleep 10` still delays for 10 seconds, so i havent broken those
<sorear>
I mean your virtio emulator code doesn't generate hw interrupts
<clever>
correct
<clever>
it doesnt even check the virtio rings
<clever>
its just barely responding to the MMIO
<clever>
HandleControlLoad(0x10010102) == 0x0
<clever>
i can also see what is kinda a bug in linux, it didnt respect the size specified in the dts
<clever>
i claimed that the virtio_input was 0x100 in size (incorrect as well), and then the driver wrote to offset 0x102!
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<clever>
sorear: adding a `enable_percpu_irq(irq, 0);` to `virtio_mmio.c`, and improving the emulators irq support, i can now get the virtio-mmio irq handler to fire on demand
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<jrtc27>
is there a reason for you to not just add a PLIC?
<jrtc27>
you'll be fighting the OS every step of the way if you try and have external interrupts that aren't external...
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<mfny1>
So ive looked around and cant find anything else like the Unmatched at same price point or lower that's available now so guess if i want RISC-V with Desktop/GPU support its the only game in town ?
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<mfny1>
Anyone have any recommendations for a miTX case for the Unmatched ?
<vagrantc>
though i'm also running mostly off of solar, so a DC-DC power supply is ideal, and they have some nice ones
<mfny1>
that seems to be a case without space for a GPU
<mfny1>
i need one with PCIE
<mfny1>
would a case with a PCIE riser work with the Unmatched ?
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<palmer>
Stove has one that fits a bunch of stuff, it's a glass/acrylic sandwich with long standoffs.
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<smaeul>
mfny1: "space for a GPU" can mean anything from a single half-height slot to multiple full height slots. I currently have my Unmatched + Radeon RX 6400 in a Mini-ITX TFX pizza box case. But you'll need something bigger with a more powerful GPU.
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<Tenkawa>
Anyone know an effective way to force a SPI hardware erase on a VF2?
<Tenkawa>
I'm taking one last look at this board before I call it unusable and it just seems if I could get the SPI/NOR emptied it might get past where it hangs up
<Tenkawa>
Since nothing else will allow interaction though its going to require a board level (grounding/chp level) I imagine if there is any hope at all..
<clever>
Tenkawa: what about the option of just unsoldering the spi flash entirely?
<Tenkawa>
clever: not an option for me
<Tenkawa>
(dexterity)
<clever>
borrow some hands?
<Tenkawa>
I'd rather "not" go that route
<Tenkawa>
The OpenSBI shouldn't be unflashable
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<clever>
are you able to compile the opensbi? printf debugging?
<clever>
figure out when and where its hanging?
<Tenkawa>
Yeah... thats easy... but I can't interact with it
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<Tenkawa>
Its locked up solid and I've posted the info any noone has any idea so far
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<Tenkawa>
Always locks up at:
<Tenkawa>
Boot HART MHPM Count : 2
<Tenkawa>
Boot HART MIDELEG : 0x0000000000000222
<Tenkawa>
Boot HART MEDELEG : 0x000000000000b109
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<clever>
and where in the source did that last line come from?
<Tenkawa>
No idea... I don't have that enabled.. thats vendor...
<clever>
you need to edit that source, and add more printf's
<clever>
to narrow down where the problem is
<Tenkawa>
I can't flash it....
<Tenkawa>
its locked up solid
<clever>
if the jumpers are working the way i expect, it should be running the copy from the sd card