sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<geist> nice!
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<another|> Whatever happened to horse creek?
<davidlt> another|, no mass availability for it IIRC
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<sorear> very interesting that this is using a third party SoC. will be looking at volume and how they differentiate it from third party boards...
<davidlt> well, this is the best
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<davidlt> This is probably a true production SoC designed by ESWIN thus not some test chip. Sipeed said they will have SOM modules with P550 in May, probably the same chip.
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<davidlt> I doubt this is a cheap board, and overall Oasis probably is a better value (minus BMC).
<bjdooks> iirc sophgo have a chip with similar cores too
* bjdooks is sad to see horsecreek seems to be lame
<davidlt> SG2380 / Oasis Gen 1
<davidlt> They just announced another spec bump for the chip. It now has 256-bit memory bus, up to 128GB.
<davidlt> They plan to use LPCAMM2 if it's available later this year. Still plan for Q4.
<davidlt> I bet it's on 12nm process too.
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<unlord> I have an SD card and df is showing 1.2G used on a partition where du shows 8.1M
<unlord> how do I figure out what is happening?
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<another|> what fs?
<another|> anything like transparent compression
<bjdooks> unlord: could the fs have a stupidly big block size?
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<unlord> another|: ext4 I think, let me look
<unlord> another|: yes, ext4
<another|> hmm... sparse files?
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<sorear> Very big disk with 1G allocated for the inode table/block bitmap/journal?
<bjdooks> or there's blocks awaiting reclamation from a file that';s been deleted but not yet unreferecned?
<sorear> or files that exist but aren't visible in the vfs or to du because you have something mounted on top of the directory?
<sorear> gnu-compatible du matches df by default for sparse files, you have to use --apparent-size to get the other behavior
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<arnd> conchuod: I'm looking at the bugfix pull requests at the moment and I'm unused about "cache: sifive_ccache: Partially convert to a platform driver" in your drivers PR. Doesn't this mean that there cannnot be any DMA before the driver subsystem is up?
<arnd> I wonder if that will cause even worse problems, e.g. if an early console driver relies on DMA
<conchuod> arnd: Is the arch_initcall that registers the cache ops not sufficiently early?
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<arnd> arch_initcall is about as early as drivers can be, but I think you can have DMA before that
<arnd> I see that drivers/dma/*.c drivers are typically either arch_initcall or subsys_initcall, so at least anything using slave dma won't come before arch_initcall
<arnd> conchuod: actually I guess the real problem is that the plic is now a device_initcall, which is much later than arch_initcall
<conchuod> arnd: ye, that's the reason the patch was required to maintain the status quo w.r.t. dma.
<conchuod> There's a bunch of drivers that do do core/postcore initcalls, if we do run into a device with really early DMA that needs this, there's at least options.
<arnd> but then no other driver at {arch,subsys,fs,rootfs,device}_initcall level can rely on DMA to work
<conchuod> If the cache ops are registered at arch level, why can't things after that use DMA?
<arnd> the device_initcall() ones may or may not work, depending on the link order
<conchuod> The part of the ccache driver that is now a platform driver is only the bits used for debugfs and by the edac driver.
<arnd> ok, I guess that makes sense. So the irq is only required for EDAC, but managing the caches works without that?
<conchuod> Yup
<arnd> ok, I'll get this merged right away then, should send it out once my branch passes the build tests
<conchuod> arnd: The interrupts are generated for corrected/uncorrected data errors in the l2.
<arnd> I still have the feeling that an irqchip driver should be initialized earlier than device_initcall() time, because otherwise every device connected to the plic gets deferred probing, but that's not a problem with the cache driver patch
<arnd> it looks like about half the platform drivers in drivers/irqchip are all builtin_platform_driver, the other ones open-code the registration using {core,postcore,arch,early}_initcall, so they are all over the place
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